JPS6465856A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6465856A
JPS6465856A JP22122687A JP22122687A JPS6465856A JP S6465856 A JPS6465856 A JP S6465856A JP 22122687 A JP22122687 A JP 22122687A JP 22122687 A JP22122687 A JP 22122687A JP S6465856 A JPS6465856 A JP S6465856A
Authority
JP
Japan
Prior art keywords
layer
wiring
twofold
aluminum
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22122687A
Other languages
Japanese (ja)
Inventor
Toshihiko Chito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP22122687A priority Critical patent/JPS6465856A/en
Publication of JPS6465856A publication Critical patent/JPS6465856A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To protect a upper wiring against exfoliation and a disconnection trouble by a method wherein the upper wiring of a twofold layer consisting of a titanium and an aluminum film is provided onto a lower wiring of a twofold layer composed of an aluminum and a titanium nitride film through the intermediary of an interlaminar insulating film and a through-hole. CONSTITUTION:An element 11 is built in a silicon substrate 1, an insulating film 2 is formed, and then an electrode contact hole 3 is provided. Next, a lower wiring 4 of a twofold layer consisting of aluminum layer 41 and a titanium nitride layer 42 is provided. Then, an interlaminar insulating film 5 is formed on the wiring 4, a through-hole 6 is provided to the film 5, and a upper wiring of a twofold layer composed of an aluminum layer 8 and a titanium layer 9 is formed through the intermediary of the through-hole 6 so as to construct a multi-layered wiring. By these processes, a upper wiring can be protected against exfoliation and a disconnection trouble.
JP22122687A 1987-09-05 1987-09-05 Semiconductor device and manufacture thereof Pending JPS6465856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22122687A JPS6465856A (en) 1987-09-05 1987-09-05 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22122687A JPS6465856A (en) 1987-09-05 1987-09-05 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6465856A true JPS6465856A (en) 1989-03-13

Family

ID=16763444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22122687A Pending JPS6465856A (en) 1987-09-05 1987-09-05 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6465856A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5365088A (en) * 1976-11-22 1978-06-10 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5365088A (en) * 1976-11-22 1978-06-10 Nec Corp Semiconductor device

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