JPS6464414A - Comparator device - Google Patents

Comparator device

Info

Publication number
JPS6464414A
JPS6464414A JP22129487A JP22129487A JPS6464414A JP S6464414 A JPS6464414 A JP S6464414A JP 22129487 A JP22129487 A JP 22129487A JP 22129487 A JP22129487 A JP 22129487A JP S6464414 A JPS6464414 A JP S6464414A
Authority
JP
Japan
Prior art keywords
turned
potential
clock
fet7p
switches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22129487A
Other languages
Japanese (ja)
Inventor
Akira Mizumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP22129487A priority Critical patent/JPS6464414A/en
Publication of JPS6464414A publication Critical patent/JPS6464414A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To execute the satisfactory comparison of small energy consumption by using a clock inverter circuit. CONSTITUTION:A switch 2 is turned on with the high potential of a clock signal phis and switches 4, 8 and 13 are turned on with the high potential of a clock signal inversion phis. Then, during the turning-on period, the starting edge is tau' delayed and a control signal phi's to turn on an FET7P, a 7N, a 12P and a 12N, the inverse of phi's are inputted to the gate of the respective FETs. Accordingly, at a time point when the switches 4, 8 and 13 are turned on and the potential of the input and output edge of respective inverter circuits goes to be VDD/2 after an tau time, the FET7P, the 7N, the 12P and the 12N are turned off and a through current is cut off. Thus, by using the clock inverter circuit, the through current at a referring potential input time is satisfactorily cut off and a power is decreased.
JP22129487A 1987-09-04 1987-09-04 Comparator device Pending JPS6464414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22129487A JPS6464414A (en) 1987-09-04 1987-09-04 Comparator device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22129487A JPS6464414A (en) 1987-09-04 1987-09-04 Comparator device

Publications (1)

Publication Number Publication Date
JPS6464414A true JPS6464414A (en) 1989-03-10

Family

ID=16764532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22129487A Pending JPS6464414A (en) 1987-09-04 1987-09-04 Comparator device

Country Status (1)

Country Link
JP (1) JPS6464414A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0385013A (en) * 1989-08-28 1991-04-10 Oki Electric Ind Co Ltd Chopper type comparator
JPH03107211A (en) * 1989-09-20 1991-05-07 Nec Corp Voltage comparator circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0385013A (en) * 1989-08-28 1991-04-10 Oki Electric Ind Co Ltd Chopper type comparator
JPH03107211A (en) * 1989-09-20 1991-05-07 Nec Corp Voltage comparator circuit

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