JPS6455890A - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JPS6455890A
JPS6455890A JP62213923A JP21392387A JPS6455890A JP S6455890 A JPS6455890 A JP S6455890A JP 62213923 A JP62213923 A JP 62213923A JP 21392387 A JP21392387 A JP 21392387A JP S6455890 A JPS6455890 A JP S6455890A
Authority
JP
Japan
Prior art keywords
thin film
sio2
gaas
mask
gaas substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62213923A
Other languages
Japanese (ja)
Inventor
Hiroshi Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62213923A priority Critical patent/JPS6455890A/en
Publication of JPS6455890A publication Critical patent/JPS6455890A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To simplify the manufacturing process and to make it possible to perform self-alignment, by providing a semiconductor substrate, wherein a II-VI compound semiconductor thin film is selectively formed on the side surface and lower surface of a step that is present on the surface, and coating the upper surface of said step with a mask. CONSTITUTION:A step is formed on the surface of a GaAs substrate 101 having a 100 surface orientation. The GaAs surface is exposed at a lower surface 102 of the step and at a side surface 103 of the step. An upper surface 104 of the step is coated with an SiO2 mask 105. In manufacturing of the step, at first, an SiO2 thin film is deposited on the GaAs substrate 101 by a thermal CVD method. Then, the SiO2 thin film at the part of the upper surface 104 of the step is made to remain, and the SiO2 thin film is etched away by a photoetching method. Finally, the remaining SiO2 thin film is used as an etching mask, and the GaAs substrate 101 is etched with sulfuric-acid based etching liquid to form a step. At this time, the GaAs surface is exposed at the lower surface 102 of the step and the side surface 103 of the step.
JP62213923A 1987-08-27 1987-08-27 Semiconductor substrate Pending JPS6455890A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62213923A JPS6455890A (en) 1987-08-27 1987-08-27 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62213923A JPS6455890A (en) 1987-08-27 1987-08-27 Semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS6455890A true JPS6455890A (en) 1989-03-02

Family

ID=16647283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62213923A Pending JPS6455890A (en) 1987-08-27 1987-08-27 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS6455890A (en)

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