JPS6453228A - Logic circuit for multiplier - Google Patents

Logic circuit for multiplier

Info

Publication number
JPS6453228A
JPS6453228A JP62208347A JP20834787A JPS6453228A JP S6453228 A JPS6453228 A JP S6453228A JP 62208347 A JP62208347 A JP 62208347A JP 20834787 A JP20834787 A JP 20834787A JP S6453228 A JPS6453228 A JP S6453228A
Authority
JP
Japan
Prior art keywords
rounding
multiplication
signal
preceding stage
optional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62208347A
Other languages
Japanese (ja)
Inventor
Toshihiro Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62208347A priority Critical patent/JPS6453228A/en
Publication of JPS6453228A publication Critical patent/JPS6453228A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize multiplication with optional accuracy and without using any complicated circuit for rounding, by supplying the rounding signal produced with an optional bit to a multiplication/addition unit circuit set at the preceding stage so that a rounding is carried out with an optional bit. CONSTITUTION:The rounding addition is carried out in the same way as the production of a partial product when '1' of the rounding signal is added to a sum input terminal 34 led from the preceding stage of the multiplication/ addition unit circuits B23, 26 and 29 set at the preceding stage where the multiplicand data is inputted. The rounding signal is produced by the bit selected by a round signal generating circuit 45 after the rounding control signals are received from the rounding control input terminals 43 and 44. As a result, the rounding position can be optionally changed by the rounding control signal and therefore the number of valid bits of the desired result of multiplication is also changed optionally.
JP62208347A 1987-08-24 1987-08-24 Logic circuit for multiplier Pending JPS6453228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62208347A JPS6453228A (en) 1987-08-24 1987-08-24 Logic circuit for multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62208347A JPS6453228A (en) 1987-08-24 1987-08-24 Logic circuit for multiplier

Publications (1)

Publication Number Publication Date
JPS6453228A true JPS6453228A (en) 1989-03-01

Family

ID=16554771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62208347A Pending JPS6453228A (en) 1987-08-24 1987-08-24 Logic circuit for multiplier

Country Status (1)

Country Link
JP (1) JPS6453228A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500812A (en) * 1993-06-14 1996-03-19 Matsushita Electric Industrial Co., Ltd. Multiplication circuit having rounding function

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222146A (en) * 1985-07-23 1987-01-30 Toshiba Corp Parallel multiplier
JPS62120535A (en) * 1985-11-20 1987-06-01 Oki Electric Ind Co Ltd Parallel multiplier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222146A (en) * 1985-07-23 1987-01-30 Toshiba Corp Parallel multiplier
JPS62120535A (en) * 1985-11-20 1987-06-01 Oki Electric Ind Co Ltd Parallel multiplier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500812A (en) * 1993-06-14 1996-03-19 Matsushita Electric Industrial Co., Ltd. Multiplication circuit having rounding function

Similar Documents

Publication Publication Date Title
JPS56147260A (en) Lsi for digital signal processing
JPS6460035A (en) Branching/inserting circuit
EP0123896A3 (en) Character and video mode control circuit
JPS6453228A (en) Logic circuit for multiplier
JPS648717A (en) Pseudo noise series code generating circuit
EP0191459A3 (en) Waveform shaping circuit
JPS5741738A (en) Digital multiplier
JPS5557948A (en) Digital adder
JPS54154964A (en) Programable counter
JPS5799062A (en) Reception circuit for data transmission
JPS5595155A (en) Operation check system for counter
JPS5685127A (en) Digital signal processor
JPS5710566A (en) Decoding circuit
JPS57150217A (en) Digital signal processing circuit
JPS5624830A (en) Phase-synchronous oscillator
JPS6412331A (en) Arithmetic circuit
JPS5792484A (en) Timing pulse generating circuit
JPS5768929A (en) Flip-flop circuit
JPS5752905A (en) Step type memory sequencer
JPS5745642A (en) Bit processing method for microcomputer
JPS56114043A (en) Code converting circuit
JPS5538684A (en) Shift register
JPS57106229A (en) Cmos multiinput storage circuit
JPS56101249A (en) Addition and subtraction system of pcm signal
JPS5629892A (en) Clear control circuit