JPS6450437U - - Google Patents

Info

Publication number
JPS6450437U
JPS6450437U JP14545487U JP14545487U JPS6450437U JP S6450437 U JPS6450437 U JP S6450437U JP 14545487 U JP14545487 U JP 14545487U JP 14545487 U JP14545487 U JP 14545487U JP S6450437 U JPS6450437 U JP S6450437U
Authority
JP
Japan
Prior art keywords
semiconductor elements
blocking
sealed
utility
registration request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14545487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14545487U priority Critical patent/JPS6450437U/ja
Publication of JPS6450437U publication Critical patent/JPS6450437U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す図、第2図は
この一実施例の作用を説明するための図、第3図
は本考案の他の一実施例を示す図、第4図は従来
例を示す図、第5図はこの従来例の作用を説明す
るための図である。 1……半導体素子、4……アイランド、5……
電極、8……ダイボンデイング材、9……封止樹
脂、11……インナーリード、13……ワイヤ、
15……接続端子、16……クラツク、17……
曲げ加工構造部、19……曲げ加工構造部、21
……封止樹脂、23……凹部。
Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram for explaining the operation of this embodiment, Fig. 3 is a diagram showing another embodiment of the invention, Fig. 4 5 is a diagram showing a conventional example, and FIG. 5 is a diagram for explaining the operation of this conventional example. 1...Semiconductor element, 4...Island, 5...
Electrode, 8... Die bonding material, 9... Sealing resin, 11... Inner lead, 13... Wire,
15...Connection terminal, 16...Crack, 17...
Bending structure section, 19... Bending structure section, 21
... Sealing resin, 23 ... Concave portion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の半導体素子を並設して封止してなる半導
体素子の実装構造において、前記半導体素子の夫
々の間に異常状態の伝播を遮断する遮断手段を設
けたことを特徴とする半導体素子の実装構造。
A semiconductor element mounting structure comprising a plurality of semiconductor elements arranged side by side and sealed, characterized in that a blocking means for blocking propagation of an abnormal state is provided between each of the semiconductor elements. structure.
JP14545487U 1987-09-25 1987-09-25 Pending JPS6450437U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14545487U JPS6450437U (en) 1987-09-25 1987-09-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14545487U JPS6450437U (en) 1987-09-25 1987-09-25

Publications (1)

Publication Number Publication Date
JPS6450437U true JPS6450437U (en) 1989-03-29

Family

ID=31414059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14545487U Pending JPS6450437U (en) 1987-09-25 1987-09-25

Country Status (1)

Country Link
JP (1) JPS6450437U (en)

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