JPS6448043U - - Google Patents

Info

Publication number
JPS6448043U
JPS6448043U JP14342787U JP14342787U JPS6448043U JP S6448043 U JPS6448043 U JP S6448043U JP 14342787 U JP14342787 U JP 14342787U JP 14342787 U JP14342787 U JP 14342787U JP S6448043 U JPS6448043 U JP S6448043U
Authority
JP
Japan
Prior art keywords
heat dissipation
dissipation fin
bonded
semiconductor device
fins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14342787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14342787U priority Critical patent/JPS6448043U/ja
Publication of JPS6448043U publication Critical patent/JPS6448043U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案を説明する為の平面図、第2図
A及び第2図Bは切込み8の形成方法を説明する
為の断面図、第3図は切込み8部分の拡大断面図
、第4図及び第5図は夫々従来例を説明する為の
平面図及び断面図である。 2は半導体チツプ、3は放熱用フイン、5は金
属細線、8は切込みである。
FIG. 1 is a plan view for explaining the present invention, FIGS. 2A and 2B are sectional views for explaining the method of forming the notch 8, FIG. 3 is an enlarged sectional view of the notch 8, and FIG. 4 and 5 are a plan view and a sectional view, respectively, for explaining a conventional example. 2 is a semiconductor chip, 3 is a heat radiation fin, 5 is a thin metal wire, and 8 is a notch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 放熱用フインにワイヤボンドを処し、モールド
後前記放熱用フインに曲げ加工が処される半導体
装置において、前記放熱用フインのモールド樹脂
端部から前記放熱用フインのボンデイングエリア
までの間に前記放熱用フインの曲げ加工による応
力を吸収する為の切込みを設けたことを特徴とす
る半導体装置。
In a semiconductor device in which a heat dissipation fin is wire-bonded and the heat dissipation fin is bent after molding, the heat dissipation fin is bonded between the molded resin end of the heat dissipation fin and the bonding area of the heat dissipation fin. A semiconductor device characterized by having notches for absorbing stress caused by bending the fins.
JP14342787U 1987-09-18 1987-09-18 Pending JPS6448043U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14342787U JPS6448043U (en) 1987-09-18 1987-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14342787U JPS6448043U (en) 1987-09-18 1987-09-18

Publications (1)

Publication Number Publication Date
JPS6448043U true JPS6448043U (en) 1989-03-24

Family

ID=31410243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14342787U Pending JPS6448043U (en) 1987-09-18 1987-09-18

Country Status (1)

Country Link
JP (1) JPS6448043U (en)

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