JPH0312429U - - Google Patents

Info

Publication number
JPH0312429U
JPH0312429U JP1989072739U JP7273989U JPH0312429U JP H0312429 U JPH0312429 U JP H0312429U JP 1989072739 U JP1989072739 U JP 1989072739U JP 7273989 U JP7273989 U JP 7273989U JP H0312429 U JPH0312429 U JP H0312429U
Authority
JP
Japan
Prior art keywords
semiconductor chip
package
semiconductor
mounting
lid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989072739U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989072739U priority Critical patent/JPH0312429U/ja
Publication of JPH0312429U publication Critical patent/JPH0312429U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例によるＦ−ＴＡＢ
実装を用いた半導体素子を示す断面図、第２図ａ
，ｂは従来のＦ−ＴＡＢ実装を用いた半導体素子
を示す断面図である。１……半導体チツプ、２…
…パツケージ、３……ＴＡＢリード、４……樹脂
材料、５……パツケージピン、６……パツケージ
フタ、７……冷却フイン、８……導電性樹脂、９
……パツケージフタの溝である。なお、図中同一
符号は同一、又は相当部分を示す。 Figure 1 shows an F-TAB according to an embodiment of this invention.
Cross-sectional view showing a semiconductor element using mounting, FIG. 2a
, b are cross-sectional views showing a semiconductor element using conventional F-TAB mounting. 1... semiconductor chip, 2...
...Package, 3...TAB lead, 4...Resin material, 5...Package pin, 6...Package lid, 7...Cooling fin, 8...Conductive resin, 9
...It's a groove in the package cage lid. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] テープを用いて半導体チツプの表面をパツケー
ジに向けて実装する方法によつて上記半導体チツ
プを実装した半導体素子において、上記半導体チ
ツプを導電性樹脂によつてダイボンドする上記パ
ツケージのふたに溝を設けたことを特徴とする半
導体素子。 In a semiconductor element in which the semiconductor chip is mounted by a method of mounting the semiconductor chip with the surface of the semiconductor chip facing the package using tape, a groove is provided in the lid of the package to which the semiconductor chip is die-bonded with a conductive resin. A semiconductor device characterized by:
JP1989072739U 1989-06-21 1989-06-21 Pending JPH0312429U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989072739U JPH0312429U (en) 1989-06-21 1989-06-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989072739U JPH0312429U (en) 1989-06-21 1989-06-21

Publications (1)

Publication Number Publication Date
JPH0312429U true JPH0312429U (en) 1991-02-07

Family

ID=31610943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989072739U Pending JPH0312429U (en) 1989-06-21 1989-06-21

Country Status (1)

Country Link
JP (1) JPH0312429U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003052527A (en) * 2001-08-08 2003-02-25 Sutooku:Kk Method for storing a pair of gifts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003052527A (en) * 2001-08-08 2003-02-25 Sutooku:Kk Method for storing a pair of gifts

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