JPS6442842A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6442842A
JPS6442842A JP62200171A JP20017187A JPS6442842A JP S6442842 A JPS6442842 A JP S6442842A JP 62200171 A JP62200171 A JP 62200171A JP 20017187 A JP20017187 A JP 20017187A JP S6442842 A JPS6442842 A JP S6442842A
Authority
JP
Japan
Prior art keywords
barrier layer
wiring
layer
multilayer wiring
residue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62200171A
Other languages
Japanese (ja)
Other versions
JPH07120654B2 (en
Inventor
Yasushi Tomijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62200171A priority Critical patent/JPH07120654B2/en
Publication of JPS6442842A publication Critical patent/JPS6442842A/en
Publication of JPH07120654B2 publication Critical patent/JPH07120654B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent defect of short-circuit of wiring caused by the residue of the exfoliated pieces of a barrier layer, and to prevent the generation of the mechanical damage on a semiconductor element by a method wherein, when a barrier layer is going to be formed in the case where a wiring is formed by plating in a multilayer wiring forming process, the barrier layer is formed by conducting a photoetching treatment. CONSTITUTION:The second photoresist film 10 is exfoliated using an organic solvent, and after an Al conductive layer 8 has been removed by wet etching, the TiN barrier layer 7 and the Ti conductive layer 6, other than the part where the second layer of wiring pattern 11 is formed, are removed by photoetching, and a multilayer wiring is formed. As the TiN barrier layer 7 can be removed without conducting mechanical exfoliation as above-mentioned, the defect of shortcircuit of wiring caused by the residue of the mechanical exfoliation can be prevented, and a multilayer wiring layer can be formed without giving mechanical damage on the semiconductor element.
JP62200171A 1987-08-10 1987-08-10 Method for manufacturing semiconductor device Expired - Lifetime JPH07120654B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62200171A JPH07120654B2 (en) 1987-08-10 1987-08-10 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62200171A JPH07120654B2 (en) 1987-08-10 1987-08-10 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6442842A true JPS6442842A (en) 1989-02-15
JPH07120654B2 JPH07120654B2 (en) 1995-12-20

Family

ID=16419973

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62200171A Expired - Lifetime JPH07120654B2 (en) 1987-08-10 1987-08-10 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH07120654B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH038337A (en) * 1989-06-06 1991-01-16 Fujitsu Ltd Manufacture of semiconductor device
JP2021070230A (en) * 2019-10-31 2021-05-06 ローム株式会社 Method for forming heat storage layer and method for manufacturing thermal print head

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56105653A (en) * 1980-01-28 1981-08-22 Seiko Instr & Electronics Ltd Gold bump forming method of semiconductor device
JPS58102542A (en) * 1981-12-15 1983-06-18 Seiko Instr & Electronics Ltd Manufacture of bump electrode

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56105653A (en) * 1980-01-28 1981-08-22 Seiko Instr & Electronics Ltd Gold bump forming method of semiconductor device
JPS58102542A (en) * 1981-12-15 1983-06-18 Seiko Instr & Electronics Ltd Manufacture of bump electrode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH038337A (en) * 1989-06-06 1991-01-16 Fujitsu Ltd Manufacture of semiconductor device
JP2021070230A (en) * 2019-10-31 2021-05-06 ローム株式会社 Method for forming heat storage layer and method for manufacturing thermal print head

Also Published As

Publication number Publication date
JPH07120654B2 (en) 1995-12-20

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