JPS57112065A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57112065A
JPS57112065A JP55187276A JP18727680A JPS57112065A JP S57112065 A JPS57112065 A JP S57112065A JP 55187276 A JP55187276 A JP 55187276A JP 18727680 A JP18727680 A JP 18727680A JP S57112065 A JPS57112065 A JP S57112065A
Authority
JP
Japan
Prior art keywords
film
region
resist
layer
poly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55187276A
Other languages
Japanese (ja)
Other versions
JPS5837701B2 (en
Inventor
Shinya Sudo
Toshio Takai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55187276A priority Critical patent/JPS5837701B2/en
Publication of JPS57112065A publication Critical patent/JPS57112065A/en
Publication of JPS5837701B2 publication Critical patent/JPS5837701B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To improve yield of manufacture of a device such as an EPROM by a method wherein a single-layer region and an upper layer of a double-layer region of a film such as poly-Si which is to be processed are patterned and the single- layer region is covered by resist of a different property to pattern the lower layer using the upper layer as a mask. CONSTITUTION:In the case of, for instance, an EPROM, in a cell region 100 two layers of poly-Si films 21, 22, are formed, holding an insulating layer 3 between then, and in a peripheral circuit region 200 the first poly-Si film 21 is formed, on a substrate 1 respectively with a gate film between the poly-Si film 21 and the substrate 1. After the film 22 of the region 100 and the film 21 of the region 200 are patterened by forming a resist film 42, the region 200 is covered by a resist film 41 and the film 21 of the region 100 is patterened into the same pattern as the film 22 by the resist film 42. If, for instance, the resist film 42 is negative type, the resist film 41 should be of a different property from the film 42, for instance, positive type. With above configuration, when the resist film 41 has a defect, if can be removed selectively and recovered, and solderability of the resist laminated portion is improved, so that the yield of the photo process is increased.
JP55187276A 1980-12-29 1980-12-29 Manufacturing method of semiconductor device Expired JPS5837701B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55187276A JPS5837701B2 (en) 1980-12-29 1980-12-29 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55187276A JPS5837701B2 (en) 1980-12-29 1980-12-29 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57112065A true JPS57112065A (en) 1982-07-12
JPS5837701B2 JPS5837701B2 (en) 1983-08-18

Family

ID=16203157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55187276A Expired JPS5837701B2 (en) 1980-12-29 1980-12-29 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5837701B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3540422A1 (en) * 1984-11-26 1986-05-28 Sgs Microelettronica S.P.A., Catania METHOD FOR PRODUCING INTEGRATED STRUCTURES WITH NON-VOLATILE STORAGE CELLS HAVING SELF-ALIGNED SILICONE LAYERS AND RELATED TRANSISTORS
JPH023269A (en) * 1988-01-04 1990-01-08 Sgs Thomson Microelectron Sa Manufacture of integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3540422A1 (en) * 1984-11-26 1986-05-28 Sgs Microelettronica S.P.A., Catania METHOD FOR PRODUCING INTEGRATED STRUCTURES WITH NON-VOLATILE STORAGE CELLS HAVING SELF-ALIGNED SILICONE LAYERS AND RELATED TRANSISTORS
DE3540422C2 (en) * 1984-11-26 2001-04-26 Sgs Microelettronica Spa Method for producing integrated structures with non-volatile memory cells which have self-aligned silicon layers and associated transistors
JPH023269A (en) * 1988-01-04 1990-01-08 Sgs Thomson Microelectron Sa Manufacture of integrated circuit

Also Published As

Publication number Publication date
JPS5837701B2 (en) 1983-08-18

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