JPS6436059A - Lead frame of semiconductor device - Google Patents
Lead frame of semiconductor deviceInfo
- Publication number
- JPS6436059A JPS6436059A JP19010187A JP19010187A JPS6436059A JP S6436059 A JPS6436059 A JP S6436059A JP 19010187 A JP19010187 A JP 19010187A JP 19010187 A JP19010187 A JP 19010187A JP S6436059 A JPS6436059 A JP S6436059A
- Authority
- JP
- Japan
- Prior art keywords
- tip parts
- inner leads
- prevented
- melting
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE:To prevent inner leads from being deformed and being contaminated by a gas so as to improve reliability of a semiconductor device, by using a low-melting-point glass to hold tip parts, which are out of a plurality of inner leads and at least face a tab, on their united states. CONSTITUTION:A low-melting point glass 8 is stuck in a square frame shape on a rear side of a semiconductor substrate at tip parts of inner leads 3 which face a tab 2. This low-melting-point glass 8 is partially melted and interposed between relatively adjacent inner leads 3. The tip parts of the respective inner leads 3 are united solidly to each other and held by this low-melting-point glass 8. The tip parts, which are mechanically weakest, can be prevented from being deformed and besides positions of the tip parts and a dimension of an interval between adjacent leads can be prevented from being varied. Wires connected between a semiconductor element mounted on the tab 2 and the tip parts of the inner leads 3 can be bonded suitably, and opening defect during the bonding process can be prevented. The adjacent leads can be also prevented from short- circuiting to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19010187A JPS6436059A (en) | 1987-07-31 | 1987-07-31 | Lead frame of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19010187A JPS6436059A (en) | 1987-07-31 | 1987-07-31 | Lead frame of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6436059A true JPS6436059A (en) | 1989-02-07 |
Family
ID=16252392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19010187A Pending JPS6436059A (en) | 1987-07-31 | 1987-07-31 | Lead frame of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6436059A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5176366A (en) * | 1989-10-20 | 1993-01-05 | Texas Instruments Incorporated | Resin-encapsulated semiconductor device package with nonconductive tape embedded between outer lead portions |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516439A (en) * | 1978-07-24 | 1980-02-05 | Hitachi Ltd | Resin seal semiconductor device |
| JPS5858345B2 (en) * | 1974-11-14 | 1983-12-24 | ジ アツプジヨン カンパニ− | Preparation of esters of PGE↓2 analogs |
| JPS60227454A (en) * | 1984-04-26 | 1985-11-12 | Nec Corp | Lead frame for semiconductor element |
-
1987
- 1987-07-31 JP JP19010187A patent/JPS6436059A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5858345B2 (en) * | 1974-11-14 | 1983-12-24 | ジ アツプジヨン カンパニ− | Preparation of esters of PGE↓2 analogs |
| JPS5516439A (en) * | 1978-07-24 | 1980-02-05 | Hitachi Ltd | Resin seal semiconductor device |
| JPS60227454A (en) * | 1984-04-26 | 1985-11-12 | Nec Corp | Lead frame for semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5176366A (en) * | 1989-10-20 | 1993-01-05 | Texas Instruments Incorporated | Resin-encapsulated semiconductor device package with nonconductive tape embedded between outer lead portions |
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