JPS6432528A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS6432528A
JPS6432528A JP62189100A JP18910087A JPS6432528A JP S6432528 A JPS6432528 A JP S6432528A JP 62189100 A JP62189100 A JP 62189100A JP 18910087 A JP18910087 A JP 18910087A JP S6432528 A JPS6432528 A JP S6432528A
Authority
JP
Japan
Prior art keywords
load
output
goes
drive
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62189100A
Other languages
Japanese (ja)
Inventor
Hatsuhide Igarashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62189100A priority Critical patent/JPS6432528A/en
Publication of JPS6432528A publication Critical patent/JPS6432528A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To attain high-speed operation by connecting a drive transistor(TR) and a load TR between a power supply and a ground potential in series and inputting an inverted signal at an output terminal to a gate of the load TR. CONSTITUTION:When an input goes to '1', the drive TR2 is turned on and its output is switched to a low level. In this case, the output of the inverting amplifier comprising TRs 3, 4 goes to '1' and an output current flows to a load TR. When the input goes to '0', the drive TR2 is turned off and the output of the logic circuit is shifted to a high level. When the level exceeds a logic threshold value when the inverting amplifier consisting of the TRs 3, 4 is viewed as an inverter exceeds a logical threshold value, the gate voltage of the load TR1 goes immediately to '0' and the current no longer flows. Thus, the ideal state is attained as the load characteristic and the switching speed is quickened further.
JP62189100A 1987-07-28 1987-07-28 Logic circuit Pending JPS6432528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189100A JPS6432528A (en) 1987-07-28 1987-07-28 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189100A JPS6432528A (en) 1987-07-28 1987-07-28 Logic circuit

Publications (1)

Publication Number Publication Date
JPS6432528A true JPS6432528A (en) 1989-02-02

Family

ID=16235353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189100A Pending JPS6432528A (en) 1987-07-28 1987-07-28 Logic circuit

Country Status (1)

Country Link
JP (1) JPS6432528A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4983759A (en) * 1972-12-15 1974-08-12
JPS61219217A (en) * 1985-03-26 1986-09-29 Nippon Telegr & Teleph Corp <Ntt> Semiconductor logic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4983759A (en) * 1972-12-15 1974-08-12
JPS61219217A (en) * 1985-03-26 1986-09-29 Nippon Telegr & Teleph Corp <Ntt> Semiconductor logic circuit

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