JPS57125525A - Logical circuit - Google Patents
Logical circuitInfo
- Publication number
- JPS57125525A JPS57125525A JP56011225A JP1122581A JPS57125525A JP S57125525 A JPS57125525 A JP S57125525A JP 56011225 A JP56011225 A JP 56011225A JP 1122581 A JP1122581 A JP 1122581A JP S57125525 A JPS57125525 A JP S57125525A
- Authority
- JP
- Japan
- Prior art keywords
- output
- phase
- short
- circuit current
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Landscapes
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Abstract
PURPOSE:To prevent exceesive output short-circuit current, by controlling an output circuit through the logic between the output and an input signal to the output circuit. CONSTITUTION:N channel MOS transistors (TRs) are employed. The input signal and output to the TR11 are in-phase and those to the TR12 are in opposite phase. Thus, at normal operation, two inputs to an exclusive logical sum 15 are always in-phase and the output is kept at a low level. On the other hand, when the output terminal is connected to the power supply or ground, the said relation is inversed, resulting in operating the exclusive logical sum 15. For example, when the output is at high level and the output terminal is connected to ground, since the input to the output and 11 are in opposite phase, the output of the sum 15 is at high level, the MOSTR13 lowers the input sigal to the 11 to a low level, and the MOSTR11 is turned off, allowing to stop short-circuit current. The short-circuit current can be prevented by similar operation, in case of the inverse state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56011225A JPS57125525A (en) | 1981-01-28 | 1981-01-28 | Logical circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56011225A JPS57125525A (en) | 1981-01-28 | 1981-01-28 | Logical circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57125525A true JPS57125525A (en) | 1982-08-04 |
Family
ID=11772009
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56011225A Pending JPS57125525A (en) | 1981-01-28 | 1981-01-28 | Logical circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57125525A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57178425A (en) * | 1981-04-10 | 1982-11-02 | Tektronix Inc | Protecting circuit for data driver |
JPH0369209A (en) * | 1989-08-08 | 1991-03-25 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
JP2007267194A (en) * | 2006-03-29 | 2007-10-11 | Fujitsu Ltd | Input/output device and method of controlling same |
JP2010098740A (en) * | 2008-10-20 | 2010-04-30 | Visteon Global Technologies Inc | High-side driver including ground protection |
-
1981
- 1981-01-28 JP JP56011225A patent/JPS57125525A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57178425A (en) * | 1981-04-10 | 1982-11-02 | Tektronix Inc | Protecting circuit for data driver |
JPH033971B2 (en) * | 1981-04-10 | 1991-01-21 | Tektronix Inc | |
JPH0369209A (en) * | 1989-08-08 | 1991-03-25 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
JP2007267194A (en) * | 2006-03-29 | 2007-10-11 | Fujitsu Ltd | Input/output device and method of controlling same |
JP2010098740A (en) * | 2008-10-20 | 2010-04-30 | Visteon Global Technologies Inc | High-side driver including ground protection |
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