JPH0369209A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the erroneous connected of a circuit to be connected with an output terminal or circuit destruction caused by timing deviation, etc., by outputting a dissidence detection signal and making the output impedance of an output buffer circuit high when the data of an input end in the output butter circuit is dissident with the data of an output terminal. CONSTITUTION:During a period Ta, at first, when a data latch signal DL is set in a low level state and the level of an output control signal OC is made high, an output signal DO of a delay circuit 31 is a high level while being delayed only for decade time t1. Accordingly, the level of an output AO from an AND gate 4 is made high and the output buffer circuit 2 is turned to an active state. At such a time, output data DT2 of a latch circuit 1 to be inputted to an exclusive OR gate 32 are compared with data OUT of an output terminal TM. When the data are coincident, a detection signal EO at the low level is outputted and when the data are dissident, the detection signal EO at the high level is outputted. Then, when the data are dissident, the level of a dissidence detection signal UE is made low and the level of the output AO from the AND gate 4 is made low. Afterwards, transistors T1 and T2 of the output buffer circuit 2 are turned OFF so that an over current can be prevented from flowing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device equipped with a 3-state output buffer circuit.

[Conventional technology]

Three-state output buffers are often used in output sections that transmit signals from semiconductor integrated circuit devices to the outside.

Conventionally, this type of semiconductor integrated circuit device, as shown in FIG. 3, includes a latch circuit 1 that latches and outputs (DT2) data DTI input by a data latch signal DL;
When the output control signal OC is at a high level, transmitting the output data DT2 of the latch circuit 1 to the output terminal TMO to the external circuit;
When the output control signal OC is at a low level, the transistor TI,
The configuration includes a 3-state output buffer circuit 2 in which T2 is turned off and the output impedance is set to high impedance.

Next, the operation of this circuit will be explained.

The input data input terminal is latched by the latch circuit 1 by the data latch signal DL and transmitted to the output buffer circuit 2. At this time, if the output control signal OC is at a high level, the output buffer circuit 2 is activated and the latch circuit is activated. The output data DT2 of 1 is output to the output terminal TMO. Conversely, if the output control signal OC is at a low level, the transistors TI and T2 of the output buffer circuit 2 are turned off, and the output impedance of the output buffer circuit as seen from the output terminal TMo becomes a high impedance state.

This output buffer circuit 2 normally has an output terminal TM.

connected to external circuitry.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit device described above, the output data DT2 of the latch circuit l is left unchanged in the output buffer circuit 2, and
This output terminal TM is normally configured to be connected to an external circuit, so if the output terminal TMo is mistakenly connected to the power supply line or ground line, or due to a timing difference with the connected single-chip microcomputer, etc., the output terminal Even if a short circuit occurs, the CPU cannot detect it, so there is a drawback that the output buffer circuit 20 may be destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that can prevent circuit breakdown of an output buffer circuit and notify a user of a malfunction.

[Means to solve the problem]

A semiconductor integrated circuit device of the present invention includes a latch circuit that latches and outputs transmitted data at a predetermined timing, and a second latch circuit that transmits output data of the latch circuit to an output terminal when an output control signal is at a first level. an output buffer circuit whose output impedance becomes high impedance when the output impedance is at a level of and control means for setting the output impedance of the output buffer circuit to a high impedance when the output buffer circuit is outputted.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

This embodiment includes inverters 1 to 3 and connects the data input terminal transmitted to the data input terminal to the data latch signal DL.
a latch circuit 1 that latches and outputs (DT2) according to
It is equipped with gate circuits Gl, G2, an inverter error, and transistors TI, T2. When the output control signal OC inputted through the AND gate 4 is at a high level, the output data DT2 of the latch circuit 1 is transmitted to the output terminal TMo, an output buffer circuit 2 in which the transistors TI and T2 are turned off when the level is high, and the output impedance becomes high impedance;
Delay circuit 31, exclusive OR gate 32, and three-man NA
The output data DT of the latch circuit 1 includes an ND gate 33.
2 and the data (OUT) of the output terminal TM, and when there is a mismatch, a mismatch detection circuit 3 outputs a mismatch detection signal UE, and when the mismatch detection signal UE is output, it masks the output control signal 0E and sets it to a low level. and output buffer circuit 2
The configuration includes an AND gate 4 as a control means for setting the output impedance of the output impedance to a high impedance.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of this embodiment.

In Fig. 2, the period of mismatch detection operation in the initial state when the power supply line or ground line is mistakenly connected to the output terminal TMO is the mismatch detection operation due to a timing difference with the tri-connected single-chip microcomputer. The period of time is indicated by Tb.

In the period Ta, first, when the data latch signal DL is in a low level state, when the output control signal OC is set to a high level, the output signal Do of the delay circuit 31 becomes high level with a delay of delay time tl, so that the previous period The mismatch signal UE is at a high level, so the output AO of the AND gate 4 is at a high level, and the output buffer circuit 2 becomes active.

In this case, the delay time tl of the delay circuit 31 may be any time required until the output control signal OC becomes high level and data is taken in.

At this time, the output data DT2 of the latch circuit 1 and the output terminal TM are input to the exclusive OR gate 32.

is compared with the data OUT, and if they match, the level is low,
If there is a mismatch, a high level detection signal EO is output, and if there is a mismatch, the mismatch detection signal UE is set to a low level, and the output AO of the AND gate 4 is set to a low level, and the output buffer circuit 2
transistor TI.

Turn off T2 to prevent excessive current from flowing.

Further, during period Tb, when high level or low level data DT1 is input to the data input terminal, the data DTI is taken into the latch circuit 1 by the rising edge of the data latch signal DL and output as data DT2.
The signal is transmitted to the external output terminal TMa via the output buffer circuit 2.

At the same time, by being input to the exclusive OR gate 32, the output data DT2 of the latch circuit l and the output terminal TMO
The detection signal EO is compared with the data OUT, and if they match, a low level detection signal EO is output, and if they do not match, a high level detection signal EO is output.

At this time, the output data DT2 of the latch circuit 1 and the output data OUT of the output buffer circuit 2 are
A difference occurs by the data propagation time t3, during which a high-level detection signal EO is output as a mismatch, but since the period t2 is masked by the inverted signal DL of the data latch signal DL, false detection due to the data propagation time difference occurs. is prevented.

When the data latch signal DL rises, its inverted signal ■
goes from a low level to a high level, and the mismatch detection signal UE, which is the output signal of the NAND gate 33, is determined by the detection signal EO. If there is a mismatch, the detection signal EO goes to a high level and the output signal (UE) of the NAND gate 33 goes to a low level. As a result, the output signal AO of the AND gate 4 becomes low level and turns off the transistors Tl' and T2 of the output buffer circuit 2.

Moreover, if the mismatch detection signal UE of the output signal of the NAND gate 33 is configured as a CPU interrupt signal,
It is also possible to notify the user of the discrepancy.

〔Effect of the invention〕

As explained above, the present invention is configured to output a mismatch detection signal and set the output impedance of the output buffer 7 circuit to a high impedance when the data at the input end of the output buffer circuit and the data at the output terminal do not match. This has the effect of being able to prevent circuit damage due to incorrect connection or timing deviation of the circuit connected to the output terminal, and to notify the user of any connection failure.

3... Mismatch detection circuit, 4... AND
Gate, 31...Delay circuit, 32...
Exclusive OR gate, 33...NAND gate, Gl, G2...Gate circuit, 11-Step 5...
...Inverter, Tl, T2...Transistor, TM, ...Output terminal.

Claims (1)

[Claims] A latch circuit that latches and outputs transmitted data at a predetermined timing; and a latch circuit that transmits the output data of the latch circuit to an output terminal when the output control signal is at a first level, and whose output impedance is high when the output control signal is at a second level. an output buffer circuit serving as an impedance; a mismatch detection circuit that compares the output data of the latch circuit with the data of the output terminal and outputs a mismatch detection signal when they do not match; and a mismatch detection circuit that outputs a mismatch detection signal when the mismatch detection signal is output; 1. A semiconductor integrated circuit device comprising: control means for setting the output impedance of the circuit to a high impedance.