JPS61269515A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To synchronize surely an input signal supplied asynchronously and to fetch the result by using an intermediate level detection circuit composing of two inverter circuits and a coincidence/dissidence circuit so as to detect an intermediate level of the input signal. CONSTITUTION:An input signal D from an external terminal is synchronized with an internal clock signal CK via a C-MOS inverter circuit IV1 and transmission gate MOSFETs Q1, Q2 and fetched by an output side node N1 composing of the FETs Q1, Q2. The signal from the node N1 is fed to a C-MOS inverter circuit IV3 having a comparatively high logic threshold voltage and a CMOS inverter circuit IV4 having a comparatively low logic threshold voltage. The output signal of the circuits IV3, IV4 is fed to an exclusive NOR circuit ENOR, where coincidence/dissidence of both the output levels is decided. The output of the circuit ENOR is fed to a gate of the MOSFETQ3 and when dissidence is decided, the FETQ3 is turned on and the output is pulled up to a high level.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and for example, to a technology that is effective when used in an input circuit of a digital integrated circuit device to which an asynchronous external signal is supplied. It is.

[Background technology]

Advances in semiconductor integrated circuit technology have made it possible to incorporate advanced information processing functions into l-chip semiconductor integrated circuit devices, making it possible to synchronize asynchronous signals with internal signals of semiconductor integrated circuits. It has become necessary.

As a circuit for synchronizing such asynchronous signals, the fifth
The flip-flop circuit shown in the figure is
It is known from the publication No. 36418. This flip-flop circuit consists of two NORs (NOR) in latch form.
) Gate circuit G3. By changing the logic threshold voltage of G4, NAND gate circuits Gl and G
This is to converge the intermediate level input through 2 to a high level or a low level.

However, in such a level-sensing flip-flop circuit, if the input signal changes at the moment the clock expires, an undefined level will be taken in, and the intermediate level will cause one of the NOR gates to be near the logic threshold voltage of circuit G3 or G4. If so, there is a problem that since a positive feedback loop is formed, there is a possibility that oscillation will occur around the logic threshold voltage.

[Purpose of the invention]

'An object of the present invention is to provide a semiconductor integrated circuit device having an input circuit that reliably synchronizes and takes in input signals supplied asynchronously without causing abnormal operation of the internal circuit.

The above-mentioned objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical aspects of the invention disclosed in this application is as follows.

That is, the intermediate level of the input signal is detected by an intermediate level detection circuit consisting of two inverter circuits with different logic threshold voltages and a match/mismatch circuit, and the input level is fixed to the high level or low level side by the detection signal, and the intermediate level is fixed to the high level or low level side. This effectively invalidates the acceptance of this.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of an input circuit for synchronizing asynchronous signals.

Each circuit element in the figure is a well-known 0MO3 (complementary MO5>
Depending on the manufacturing technology of the integrated circuit, but not particularly limited, 1
It is incorporated into a digital integrated circuit device formed on a semiconductor substrate such as solid quasi-crystalline silicon.

An asynchronous input signal from an external terminal is taken into the circuit via a CMOS inverter circuit IVI. The output signal of this inverter circuit IVI is transmitted from the parallel P-channel and N-channel transmission gates MO3FETQ1.
' Synchronized to internal clock signal CK via Q2.

That is, the internal clock signal CK is supplied to the gate of the N-channel MO3FETQ2, and the clock signal G is supplied to the gate of the P-channel MO3F'ETQI.
K is inverted and supplied by an inverter circuit IV2.

During the period when the clock signal CK is at high level, these (7)
MO5FE'l'Ql and G2 are turned on, and an external signal is transmitted through the inverter circuit tvi.

Then, at the timing when the clock signal GK changes from high level to low level, the above MOS F E 'r
By turning off Q1 and G2, the external signal synchronized with the timing is taken into the output node Nl.

If this imported external signal is at an intermediate level, an undefined rail is supplied to the internal circuit that receives it, causing a large through current in the 0M03 circuit.
Oscillation occurs in level-sensitive preamp-flop circuits.

In order to avoid such undesired operation, in this embodiment, an intermediate level detection circuit and MO3 consisting of the following circuits are used.
FETQ3 is added. That is, the signal at the node N1 has a relatively high logic threshold voltage VTI.
and a CMOS inverter circuit IV4 having a relatively low logic threshold voltage VT2. The output signals of these inverter circuits IV3 and IV4 are sent to the exclusive OR NOT circuit E.
It is supplied to the NOH, where it is determined whether the power levels of both rivers match or do not match. The output signal N2 of the exclusive OR NOT circuit ENOH as this match/mismatch circuit is connected to the node N
1 and the power supply voltage Vcc, and is supplied to the gate of a pull-up P-channel MO3IETQ3.

This exclusive □ OR negation circuit ENOR outputs a mismatch output signal of low level (logic "0") when the two signals do not match, in other words, when one of the two signals is high level and the other is low level. The node N1 is sent to an internal circuit (not shown) via a CMOS inverter circuit v5.

Note that the pull-up MO3FET Q3 is set so that its operating impedance has a relatively large value when it is turned on. In other words, MO3F
ETQ3 is connected to node N even when it is turned on.
It is made to have a large impedance so that the signal level of 1 is determined according to the output signal of the CMOS inverter circuit IVI. This also applies to the second embodiment described later.

An example of the operation of this embodiment circuit will be explained with reference to the timing diagram of FIG.

MO3FB'l'Q] and Q2 are turned off at the timing when clock No. 48 cK changes from high level to low level. At this timing, the asynchronous signal via the CMOS inverter circuit IVI changes from high level to low level and is in the intermediate level region between the rosin threshold voltages VT1 and VT2 of the inverter circuits IV3 and IV4. Then, the output signal of the inverter circuit IV3 is set to a high level, and the output signal of the inverter circuit IV4 is set to a low level. This causes the exclusive OR NOT circuit ENOR to send out a low-level mismatch signal at its output N2. P-channel MO3FETQ3 is turned on by the low level of this output signal N2,
The intermediate level is pulled up to a high level such as power supply voltage Vcc. As a result, while the clock signal CK is at a low level, the internal signal (N1) taken in is kept at an intermediate level, causing an undesired through current in the inverter circuit IV5, etc., and a level-sensitive flip-flop (not shown). Undesirable oscillations and the like can be prevented from occurring in the circuit.

When the next clock signal CK arrives, the external signal that is in the process of changing is reliably brought to a low level, so that signal can be taken in in synchronization with the low level of this clock signal CK. In order to do this, the clock signal GK is applied with a cycle that is approximately 1/2 or less of the minimum cycle of the asynchronous external signal.

In addition, in the internal circuit, at the timing when the clock signal CK is set to low level, the exclusive OR NOT circuit E is activated.
It may be possible to determine whether the signal at the node N1 is valid or invalid by determining the level of the output signal N2 of the NOH. That is, at the above timing, the exclusive OR NOT circuit E
If the NOH output signal N2 is at a low level, the signal at the node Nl is invalidated, and the signal at the node Nl is taken in in the next cycle. This allows asynchronous signals to be captured at high speed.

[Embodiment 2] FIG. 3 shows a circuit diagram of another embodiment of the present invention.

In this embodiment, a clocked inverter circuit is used as the input gate circuit. That is, the asynchronous signal supplied from the external terminal is P channel MO3FB'T'
QII and the gate of N-channel MO8FET Q12. The source of the MO5FET QII is a P-channel MO3FET whose gate is supplied with a clock signal inverted by the inverter circuit IV2 in the same way as described above.
Power supply voltage Vcc is supplied via QIO. In addition, the source of the MO3FETQ13 has a clock signal CK.
is supplied to the gate of N-channel MO3FETQ12
The ground potential of the circuit is supplied through the circuit. by this,
Both MO3FETQI 1 forming the above inverter circuit
and Q12 are put into the 'ζ operating state in synchronization with the clock signal CK.

Furthermore, by providing an inverter circuit at the output of the exclusive OR NOT circuit ENOH, an inverted signal N2° is formed and an N-channel pull-down MO3FE'l
"Q14 is provided between the node N1 and the ground potential point of the circuit. In this embodiment, if the level of the signal (node Nl) taken in through the clocked inverter circuit is at an intermediate level, the pull-down MO5FETQI4
is turned on, the intermediate level is changed to the low level (l
It is something that fixes it.

The operation of this embodiment is substantially equivalent to that of the circuit shown in FIG. 1, so a description thereof will be omitted.

[Embodiment 3] FIG. 4 shows a circuit diagram of another embodiment of the present invention.

In this embodiment, when an asynchronous signal supplied from an external terminal is taken into node N1, when the signal changes (intermediate level)
This is to prevent the inconvenience of delaying the level change when the similar pull-down MO3F ETQ3 is turned on. In other words, when the clock signal CK is at a high level, the similar pull-down MO3F ETQ3 is turned on.
When FE, TQ1 and Q2 are in the on state, at the intermediate level where the asynchronous signal at the node N1 changes from low level to high level, the pull town MOS FET Q3' is in the on state as in the previous embodiment. When this happens, the rise to high level is delayed. Therefore, the output signal of the above-described logical OR NOT circuit BNOR is outputted via the NOR gate circuit NOR. This NOR gate circuit NOR has a clock signal CKI (
In this embodiment, by inverting the output signal of the inverter circuit IV2 by the inverter circuit IV6,
(forming a non-inverted clock signal CKI).

As a result, when the clock signal CKI is at a high level, the output signal N2'' of the NOR gate circuit NOH is set to a low level regardless of the output signal of the exclusive OR NOT circuit ENOR.Such a low level signal N2° As a result, pull-down MO5FE"l'Q3° is turned off. Therefore, it is possible to prevent the signal change operation from being slowed down by the pull-down MOS FET during the asynchronous signal capture operation. therefore,
MO3FETQ3° can lower the impedance when CKI is at low level than in other embodiments, and can perform pull-down at high speed.

Further, in this embodiment, an inverter circuit IV similar to the above
5's output signal D° to a similar transmission gate MO3FE'l''
, 14 and Q5, the data is captured by the clock signal CK2. In other words, in this embodiment, two-phase clock signals CKl and CK2 are used, and the data is sent to an internal circuit (not shown) in synchronization with the clock signal CK2. It forms the synchronization signal to be supplied.

〔effect〕

(1) By using an inverter circuit with two different logic threshold voltages and a match/mismatch circuit, it is possible to detect that a mixed asynchronous signal is at an intermediate level. By pulling-amplifying or pulling down the intermediate level using this detection output, it is possible to prevent undesired abnormal operations such as through current and oscillation in the internal circuit.

(2) The above +11 provides the effect that asynchronous external signals can be taken in quickly and reliably without waiting until abnormal operations such as oscillation stop naturally. In other words, an external signal that changes at a timing asynchronous to the clock signal can be accurately captured in the time equivalent to two clock signals at most. This results in
In a digital control system to which this invention is applied, the effect of speeding up the response to signals that are not synchronized with the internal clock (interrupts and signals from input/output devices) can be obtained.

(3) Coincidence/non-sand detection at the timing of asynchronous signal capture using a clock signal By checking the IN signal, it is possible to identify whether the captured signal is valid or invalid, thereby capturing the asynchronous signal in the shortest possible time. This has the effect of being able to.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. The match/mismatch circuit is
In addition to the exclusive OR NOT circuit, any circuit that performs substantially the same operation as the exclusive OR NOT circuit may be used. For example, the exclusive OR NOT circuit ENOR in FIG. 1 is an inverter circuit!
(2) It can be replaced with a Nant gate circuit which receives the output of 3 and the negative output of the inverter circuit IV4. In FIG. 1, the circuit ENOR can be omitted. In this case, for example, the output of the inverter circuit I V 40) is MO
3FETQ:M) Directly 4' to Game 1-! The output of the inverter circuit IV3 is inverted, and an additional MOSF
Supplied to the gate of ET. Such additional MOSFET
is connected in series with MO3FETQ3. In addition to the CMOS circuit, each circuit may be configured only with an N-channel MO3FET or a P-channel MOSFET 'l'.

(Field of Application) The present invention can be widely used in various semiconductor integrated circuit devices including an input circuit that synchronizes asynchronous signals.

[Brief explanation of drawings]

Fig. 1 is an example of the present invention, a circuit diagram showing fc,
The figure is a timing diagram for explaining an example of its operation. Figure 3 is a circuit diagram showing another embodiment of the invention. Figure 4 is a circuit diagram showing still another embodiment of the invention. FIG. 5 is a circuit diagram for explaining an example of the prior art. IVI-IVI3・, Inverter circuit, ENOR・・Exclusive OR NOT circuit Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A gate circuit having a three-state output function that takes in an input signal supplied from an external terminal asynchronously with an internal clock signal, and an output signal of the gate circuit within a predetermined level range. The gate circuit is characterized by comprising an input circuit including a detection circuit that detects whether or not the gate circuit is in the gate, and a voltage supply circuit that is activated by a detection signal of the detection circuit and fixes the output terminal of the gate circuit at a high level or a low level. Semiconductor integrated circuit device. 2. Claims characterized in that the detection circuit includes a logic gate circuit that is controlled by the clock signal and disables the transmission of the detection signal when the gate circuit is open. 2. The semiconductor integrated circuit device according to item 1.