JPS61219217A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor logic circuit which is low in power consumption and operates at a high speed and, at the same time, gives a stable DC output, by providing an inverter circuit which inputs a logical output and outputs the input after inversion and feeding back the output of the inverter circuit to the gate of a load transistor. CONSTITUTION:When any one of the input signals given to input terminals I1-I3 is high level, the signal of an output terminal 4 naturally becomes low level. When all the input signals are low level, the output of the output terminal 4 gradually rises in accordance with the ratio of all the transconductance gm(n) of (n) MOS transistors 1-3 for input to the transconductance gm(p) of a (p) MOS transistor 8 which becomes a load or the ratio of leak currents. When the value of the output exceeds the threshold of a CMOS inverter 5, the (p) MOS transistor 8 is set to a conducted condition and, thereafter, the output becomes high level in a moment. Since the condition is maintained by means of a feedback circuit through the CMOS inverter 5 when the output terminal 4 once becomes high level in such a way, this circuit becomes a stable circuit in the sense of DC.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor logic circuit that operates at low power and high speed.

(Prior art) As a conventional CMO8NOR circuit, for example, there is a circuit as shown in FIG.
December 1983 Vo1.66-CNo, 12 P, 919
FIPOS/CMO316Kbit static RAM
Written by Tatsuo Baba).

In FIG. 5, Pi~P is PMO8 (p channel M
oS transistor), N1 to N4 are nMOS (n channel MOS transistors), ■, ~I4 is an input terminal,
d is an output terminal.

In the 0MO5NOR circuit shown in FIG. 5, current flows only during a transient period when the input signal changes, and no current flows in a steady state.

Therefore, it has the characteristic that it does not require electric power in a steady state.

Further, FIG. 6 is also an example diagram of a conventional NOR circuit (described in, for example, Japanese Patent Publication No. 41579 of 1982).

In FIG. 6, a transistor P serves as a load.

is controlled by a clock control signal applied to the clock terminal 18 in synchronization with the input signal, and only when the clock control signal is applied, that is, only during operation.
Current flows through the circuit.

Therefore, this circuit also has the effect of reducing power consumption. In addition, in FIG. 6, 17 is an output terminal,
In addition, the same symbols as in FIG. 5 indicate the same parts.

[Problem that the invention seeks to solve]

However, in a circuit such as that shown in FIG.

Since nine MO8s serving as a load are connected in series, there is a problem in that the rise time of the recorder output at the time of selection becomes long, and high-speed operation is not possible.

In addition, in the circuit shown in FIG. 6, all of the input terminals I, ~, are at a low level, and the load transistor P is turned on (the clock control signal is at a low level), so that the output terminal 17 is at a high level. After the state is reached, when the clock control signal goes high and the load transistor P, turns off,
The output terminal 17 becomes floating and unstable in terms of direct current. In other words, the logic is performed only when the clock control signal is input, and the output becomes unstable in other cases.
It is necessary to provide a clock control signal while the logic is being transmitted to the final stage, and current flows through the circuit during this time, which poses problems such as insufficient power reduction.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art as described above, and to provide a semiconductor logic circuit that operates at low power and high speed and provides a stable DC output.

[Means to solve the problem]

In order to achieve the above object, in the present invention, transistors of one type among nMOS and PMO8 are used as a plurality of input transistors each receiving a plurality of input signals, and the other type is used as a load. A logic circuit using a transistor is provided with an inverter circuit that takes the logic output as an input, inverts it and outputs it, and is configured to feed back the output of the inverter circuit to the gate of the transistor of the load. .

Furthermore, in the present invention, a transistor of the same type as the load is connected in parallel with the load transistor, and the transistor is configured to temporarily have a low impedance by a high-speed trigger pulse, thereby achieving an even faster and higher level output. It is possible to realize a semiconductor logic circuit that can obtain the following.

Further, in the present invention, by providing a circuit for amplifying the logic output in addition to the above-described configuration, it is possible to increase the driving capability and realize a semiconductor logic circuit that operates at higher speed.

[Embodiments of the invention]

FIG. 1 is a diagram showing an embodiment of the basic circuit of the present invention.
The R circuit is shown.

In FIG. 1, 1 to 3 are n M O for input, respectively.
S transistors, connected in parallel with each other.

Note that the nMO8h transistors for input are connected as many as the number of input signals.

Further, 11 to I are signal input terminals.

Further, 6 is an nMOS transistor, and 7 is a 9MOS transistor, and these 6 and 7 form a CMOS inverter 5 which receives the output of the NOR circuit as input.

Further, 8 is a pMOS transistor driven by the output of the CMOS inverter 5.

Further, 14 and 15 are power supply terminals, for example, 14 is connected to the power supply voltage Vcc, and 15 is connected to the ground, or vice versa.

In the circuit shown in FIG. 1, if any one of the input signals applied to the input terminals C, -, is at a high level, the signal at the output terminal 4 naturally becomes at a low level.

Also, when all input signals are low level, output terminal 4
The output of is the transconductance gm (n) of all the input nMOS transistors 1 to 3 and the load 2
Transconductance g-( of MOS transistor 8
p) or the leakage current ratio, and when the value exceeds the threshold of the CMOS inverter 5, the
Transistor 8 becomes conductive, and then becomes high level all at once.

As described above, in the circuit shown in FIG. 1, once the output terminal 4 becomes high level, that state is maintained by the feedback circuit via the CMOS inverter 5, so that the circuit becomes extremely stable in terms of direct current.

Further, since the time during which current flows through all the circuits is only during a transient period, it is clear that the low power characteristic common to 0M08 circuits in general is maintained.

Furthermore, by combining the circuit shown in Figure 1 with high-speed trigger pulses as shown in Figures 2 and 4, which will be described later, it is possible to operate at higher speed, use less power, and obtain a stable DC output. A semiconductor logic circuit can be realized.

Next, FIG. 2 is a diagram showing a second embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts.

In the embodiment shown in FIG. 2, a transistor of the same type as the PMOS transistor 8 serving as the load in the embodiment shown in FIG. The structure is such that it temporarily enters a low impedance state.

Note that a high-speed trigger pulse is applied to the trigger input terminal 16 from a high-speed trigger pulse generation circuit (not shown), and the PMOS transistor 9 is driven by the high-speed trigger pulse.

In FIG. 2, if all of the input terminals C, - C are at low level and a trigger pulse is applied to the trigger input terminal 16, then g+w(p)>g+n(n), so the output terminal 4's output suddenly reaches a high level.

Thereafter, even if the trigger pulse applied to the trigger input terminal 16 is cut off, the output of the output terminal 4 continues to be stably maintained at a high level by feedback from the CMOS inverter 5.

FIG. 3 is an operation timing diagram of the circuit shown in FIG. 2 above.

In FIG. 3, a trigger pulse is applied at the same time as the input changes.

If all inputs are at low level, the output will be at high level, and if even one input is at high level, the output will be at low level.

As described above, in the circuit shown in FIG. 2, the output terminal 4 is short-circuited to the high potential (terminal 14) only through the PMOS transistor 9 at the time of rising.

Also, at the time of falling, the output terminal 4 is connected to the nMOS transistor 1.
Since only the stage is shorted to the low potential (terminal 15), the rise time tLH and fall time tHL are extremely fast.
can be realized.

In addition, the outline of tLH and tHL is shown by the following formula.

tLo=C/gn+ (pMO39) tut=c/gm (nMOs) In the above formula, C is the sum of the capacitance between the source and drain of the CMOS transistor and the capacitance due to wiring, etc., and gvs (pMO39) is This is the transconductance of the PMOS transistor 9.

Also, in the circuit shown in FIG. 2, the time during which the entire circuit current flows is only during a transient period, so it is clear that the low power characteristic common to 0M08 circuits in general is maintained.

Furthermore, in the circuit shown in Fig. 2, the p
It goes without saying that the device can also operate using an nMOS load, a resistor, or other charge supply circuit in place of the MO3 load.

Next, FIG. 4 shows a third embodiment of the present invention, in which the same reference numerals as in FIG. 2 indicate the same parts.

The circuit shown in FIG. 4 is a circuit that includes a logic output amplifying circuit in addition to the configuration shown in FIG. 2, thereby increasing the driving ability and operating at higher speed.

In FIG. 4, the pMOS transistor lO is a CMO
It is driven by the output of the S inverter 5.

Further, the PMOS transistor 11 has a trigger input terminal 16.
is driven by a trigger pulse from a high-speed trigger pulse generation circuit.

Further, 12 and 13 are npn type bipolar transistors.

In the circuit of FIG. 4, when all of the input terminals 11 to 1 are at a low level and a trigger pulse is applied to the pMOS transistor 11, the pMOS transistor 11 becomes conductive and the npn bipolar transistor 1
Since the high potential of the power supply terminal 14 is applied to the base electrode of 2,
The output of output terminal 4 immediately becomes high level.

Thereafter, even if the trigger pulse is cut off, the output terminal 4 continues to be kept at a high level by the feedback circuit formed by the CMOS inverter 5.

If even one of the input terminal work and ~ work is at a high level,
Any one of the input NMOS transistors 1 to 3 becomes conductive, and the output terminal 4 becomes a low level.

This low level value is npn lower than the low potential of the power supply terminal 15.
The voltage between the emitter and base of the bipolar transistor 13 becomes higher.As described above, in the circuit shown in FIG. Since it changes, it can be operated at extremely high speed.

Furthermore, since the single circuit current flows only during transient times when the input signal changes, it is clear that low power consumption is maintained.

In the first to third embodiments described above, NOR circuits have been described, but the nMOS transistors in the embodiments described above are replaced with PMOS transistors, the PMOS transistors are replaced with nMOS transistors, and the npn type bipolar transistors are replaced with pnpn arrays. It is obvious that a NAND circuit can be easily formed by changing to a type polar transistor.

〔Effect of the invention〕

As explained above, in the present invention, since the output signal is fed back to the load transistor via the inverter circuit, an extremely stable output can be obtained in terms of direct current.

Further, since the output terminal and the high-level potential and the low-level potential are both connected by parallel transistors, there is an advantage that the rising and falling times are extremely fast.

In addition, since it has low power consumption characteristic of CMO8 circuits, when applied to large-scale logic LSIs, memory LSIs, memory decoder circuits, etc., it is possible to increase the speed of these LSIs without increasing the power consumption. becomes.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are illustrations of one embodiment of the present invention, and FIG.
This figure is an operational waveform diagram of the circuit of FIG. 2, FIG. 4 is a diagram of another embodiment of the present invention, and FIGS. 5 and 6 are diagrams of an example of a conventional logic circuit. Explanation of symbols> 1 to 3...nMOS transistor 4...output terminal 5...CMOS inverter 6...nMOS transistor 7 to 11...pMOS transistor 12, 13...npn bipolar transistor 14
, 15... Power supply terminal 16... Trigger input terminal Patent Applicant: Nippon Telegraph and Telephone Public Corporation Representative Patent Attorney Junnosuke Nakamura 1'1 Figure 3 Figure 5 Figure Procedure Amendment Form Button Patent dated April 18, 1985 Agency Commissioner Manabu Shiga 1, Indication of case Patent Application No. 59617 of 1985 2, Title of invention Semiconductor logic circuit 5, Subject of amendment Drawing 6, Contents of amendment Drawing 5 is amended as attached. .

Claims (1)

[Claims] In a logic circuit that uses either nMOS or pMOS transistors as a plurality of input transistors that each receive a plurality of input signals, and uses the other type of transistor as a load, the logic output thereof is used as an input. , an inverter circuit that inverts and outputs the inverter circuit, and feeds back the output of the inverter circuit to the gate of the transistor of the load.