JPS6449423A - Complementary metal- oxide-semiconductor circuit - Google Patents

Complementary metal- oxide-semiconductor circuit

Info

Publication number
JPS6449423A
JPS6449423A JP18015488A JP18015488A JPS6449423A JP S6449423 A JPS6449423 A JP S6449423A JP 18015488 A JP18015488 A JP 18015488A JP 18015488 A JP18015488 A JP 18015488A JP S6449423 A JPS6449423 A JP S6449423A
Authority
JP
Japan
Prior art keywords
voltage
node
trs
inverter
turns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18015488A
Other languages
Japanese (ja)
Inventor
Yotsuto Derange Buiremu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JPS6449423A publication Critical patent/JPS6449423A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To enable an output to drive another gate without any intermediate buffer by pulling up the input terminal of an inverter and making no DC current flow to the inverter when both input signals are high. CONSTITUTION: When the inputs A and B are both low, neither of transistors(TR) 30 and 31 conducts, TRs 34 and 35 turn on to raise the voltage at a node 41 up to Vc C, and a TR 37 turns on to hold a line 39 almost at the earth voltage. When one of them is high, one of the TRs 30 and 31 turns on to send a zero voltage to the node 41 and a TR 38 turns on to develop the voltage Vc C at an output node 39. When both the inputs are high, both the TRs 30 and 31 turn on to supply an input signal which has dropped by a threshold voltage to the node 41. The TR 38 is cut off by feedback through a TR 40 and the DC circuit of the inverter 36 can be eliminated.
JP18015488A 1987-07-29 1988-07-19 Complementary metal- oxide-semiconductor circuit Pending JPS6449423A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US7897687A 1987-07-29 1987-07-29

Publications (1)

Publication Number Publication Date
JPS6449423A true JPS6449423A (en) 1989-02-23

Family

ID=22147346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18015488A Pending JPS6449423A (en) 1987-07-29 1988-07-19 Complementary metal- oxide-semiconductor circuit

Country Status (4)

Country Link
JP (1) JPS6449423A (en)
DE (1) DE3824504A1 (en)
FR (1) FR2618962A1 (en)
GB (1) GB2207572A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5569628A (en) * 1993-01-25 1996-10-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device fabrication method

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT398870B (en) * 1991-05-28 1995-02-27 Austria Mikrosysteme Int INTEGRATED CIRCUIT ARRANGEMENT WITH JUNCTION, MOS AND BIPOLAR TRANSISTORS
JPH07142995A (en) * 1993-06-04 1995-06-02 Xilinx Inc Small electric current inverter according to request
KR970024601A (en) * 1995-10-27 1997-05-30 김주용 Exclusive OR circuit
KR101353212B1 (en) * 2011-06-14 2014-01-22 한국과학기술원 Inverter and switching circuit having the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1252036A (en) * 1968-08-20 1971-11-03
JPS60206222A (en) * 1984-03-29 1985-10-17 Toshiba Corp Exclusive or circuit
US4620117A (en) * 1985-01-04 1986-10-28 Advanced Micro Devices, Inc. Balanced CMOS logic circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5569628A (en) * 1993-01-25 1996-10-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device fabrication method

Also Published As

Publication number Publication date
GB2207572A (en) 1989-02-01
DE3824504A1 (en) 1989-02-09
FR2618962A1 (en) 1989-02-03
GB8811528D0 (en) 1988-06-22

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