JPS6449420A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS6449420A
JPS6449420A JP62207007A JP20700787A JPS6449420A JP S6449420 A JPS6449420 A JP S6449420A JP 62207007 A JP62207007 A JP 62207007A JP 20700787 A JP20700787 A JP 20700787A JP S6449420 A JPS6449420 A JP S6449420A
Authority
JP
Japan
Prior art keywords
transistor
current
level
reversal
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62207007A
Other languages
Japanese (ja)
Inventor
Hiroshi Ideta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62207007A priority Critical patent/JPS6449420A/en
Publication of JPS6449420A publication Critical patent/JPS6449420A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To efficiently transmit the output signal of a bipolar transistor up to a high frequency, by supplying a driving current to a reversal transistor which drives an IIL gate. CONSTITUTION:A differential input signal added on input terminals 1a and 1b switches the current of a current source 17 to a collector current by a pair of transistors 13 and 14, respectively. At a time when the current of the current source 17 flows on a transistor 13, a transistor 16 is energized, and the reversal transistor 18 is set at a cut-off state, and the IIL gate 21 is set at an input H level and output L level. When a current flows on the collector of the transistor 14, since transistors 15 and 16 are set at cut-off states, the collector current of the transistor 14 becomes the base current of the transistor 18 and energizes the reversal transistor 18, thereby, the IIL gate 21 is set at an input L level and output H level.
JP62207007A 1987-08-20 1987-08-20 Interface circuit Pending JPS6449420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62207007A JPS6449420A (en) 1987-08-20 1987-08-20 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62207007A JPS6449420A (en) 1987-08-20 1987-08-20 Interface circuit

Publications (1)

Publication Number Publication Date
JPS6449420A true JPS6449420A (en) 1989-02-23

Family

ID=16532652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62207007A Pending JPS6449420A (en) 1987-08-20 1987-08-20 Interface circuit

Country Status (1)

Country Link
JP (1) JPS6449420A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114986A (en) * 1978-02-14 1979-09-07 Motorola Inc Differential singleeended converter circuit using reverse transistor
JPS59108427A (en) * 1982-12-14 1984-06-22 Toshiba Corp Interface circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114986A (en) * 1978-02-14 1979-09-07 Motorola Inc Differential singleeended converter circuit using reverse transistor
JPS59108427A (en) * 1982-12-14 1984-06-22 Toshiba Corp Interface circuit

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