JPS56153836A - Semiconductor circuit - Google Patents
Semiconductor circuitInfo
- Publication number
- JPS56153836A JPS56153836A JP5649180A JP5649180A JPS56153836A JP S56153836 A JPS56153836 A JP S56153836A JP 5649180 A JP5649180 A JP 5649180A JP 5649180 A JP5649180 A JP 5649180A JP S56153836 A JPS56153836 A JP S56153836A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- voltage
- capacity
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To realize a high-speed operation for a semiconductor circuit, by providing a means that holds the gate voltage of a transistor (TR) in an MOS driving circuit at a level higher than the power supply voltage. CONSTITUTION:The data signal (d) is supplied to the input of a delaying circuit 50 consisting of a 2-stage inverter, and the output A of circuit 50 is connected to the capacity C1. At the same time, the output D of buffer 20' is connected to the other end of C1. The level compensating transistor TR11 is connected between the output D and power source VC, and the gate of TR11 is connected to VC. In the same way, the data signal (d') is supplied to the input of a delaying circuit 60 consisting of a 2-stage inverter. And the output B of circuit 60 plus output D' of buffer 30 are connected to the capacity C2. Then the level compensating TR16 is connected between the output D' and power source VC, and the gate of TR16 is connected to VC. When the signal (d) changes from 0 to 1, the output D is charged by TR1. The voltage of output D is increased by the capacity C1 after a delay time given by the circuit 50 and reaches the voltage VC or higher. Thus the output DOUT of the output-stage buffer 40 is set quickly at 1 level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5649180A JPS56153836A (en) | 1980-04-28 | 1980-04-28 | Semiconductor circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5649180A JPS56153836A (en) | 1980-04-28 | 1980-04-28 | Semiconductor circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56153836A true JPS56153836A (en) | 1981-11-28 |
Family
ID=13028554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5649180A Pending JPS56153836A (en) | 1980-04-28 | 1980-04-28 | Semiconductor circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56153836A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5899032A (en) * | 1981-12-08 | 1983-06-13 | Toshiba Corp | Semiconductor integrated circuit |
JPS6041326A (en) * | 1984-07-17 | 1985-03-05 | Hitachi Ltd | Inverter circuit |
JPS62501739A (en) * | 1985-02-08 | 1987-07-09 | エイ・ティ・アンド・ティ・コーポレーション | Integrated circuit with variable boosted nodes |
JPH01268311A (en) * | 1988-04-20 | 1989-10-26 | Seiko Epson Corp | Semiconductor integrated device |
US6188254B1 (en) | 1998-12-22 | 2001-02-13 | Hyundai Electronics Industries Co., Ltd. | Data output buffer with high drivability in semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4998955A (en) * | 1972-12-29 | 1974-09-19 |
-
1980
- 1980-04-28 JP JP5649180A patent/JPS56153836A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4998955A (en) * | 1972-12-29 | 1974-09-19 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5899032A (en) * | 1981-12-08 | 1983-06-13 | Toshiba Corp | Semiconductor integrated circuit |
JPS6041326A (en) * | 1984-07-17 | 1985-03-05 | Hitachi Ltd | Inverter circuit |
JPS62501739A (en) * | 1985-02-08 | 1987-07-09 | エイ・ティ・アンド・ティ・コーポレーション | Integrated circuit with variable boosted nodes |
JPH01268311A (en) * | 1988-04-20 | 1989-10-26 | Seiko Epson Corp | Semiconductor integrated device |
US6188254B1 (en) | 1998-12-22 | 2001-02-13 | Hyundai Electronics Industries Co., Ltd. | Data output buffer with high drivability in semiconductor device |
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