JPS5899032A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption and to quicken the operating speed, by providing a cpacitor to a gate of a load transistor (TR) of an enhancement type inverter circuit and charging the gate when a driver TR is turned on. CONSTITUTION:The element size of depletion D type MOS TRs Q7, Q6, Q8 is selected suitably, the potential of a node N1 is set to a power supply VDD level when an input signal IN is an H level and the potential of node N2 is set to a ground level, an enhancement E type load TRQ4 is truned off, a drive TRQ5 is turned on and an output OUT goes to a L level. Positive charges of VDD are stored at the node N1 of a capacitor C. When the signal IN changes to the L level, the TRs Q7, Q8 are turned off and the node N3 goes to the H level and stored in a TRQ9. Since the gate of the TRQ4 is controlled with 2 VDD, the output level goes to the VDD rapidly, and since the TRs Q4, Q5 are of E type, the through-current flows in transient state only.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention This invention relates to MO811 integrated circuits, and more particularly to single channel z/D (enhancement/depression) integrated circuits.
Technical background of the invention and its problems regarding type semiconductor integrated circuits General j, n-channel! When driving a large load capacity in the IIE/D MO8 circuit, a buffer circuit loaded with a depletion type transistor as shown in FIG. 1 is used to reduce the signal propagation delay time. In other words, the ground point GN
A D (depression) II load transistor Q8 and an E (enhancement) type driver transistor Q are connected in series between the D and D. Then, the input signal IN is supplied to the gate of the transistor Qs via the inverter circuit NoTr to make it conductive, and the inverter circuit NOT@tN is supplied to the gate of the transistor Qs.
The input signal IN is supplied via the OT t to control conduction, and the load capacitor CL is driven by the potential at the connection point of the transistors Qs and Qx.

However, in such a configuration, when the driver transistor Q of the buffer circuit is in the on state, the load transistor Ql and the driver transistor Q! are connected from the power supply VDD to the ground point GND. Since a through current flows through the capacitor, it has the disadvantage of high current consumption.

In order to prevent the increase in current consumption due to the above-described through current, a KlE type buffer circuit as shown in FIG. 2 has been proposed. In this circuit, an E-type transistor Qs is provided in place of the D-type load transistor Q1 shown in FIG. 1. Components that are the same as those in the circuit in FIG. is omitted. According to such a configuration,
Since the load transistor is of the E type, the load transistor Q1 is in the off state when the driver transistor Qs is in the off state, and the above-mentioned through current does not flow. However, in this circuit, since the load transistor is E type, the output voltage level of the buffer circuit does not rise to the voltage l1lvDD voltage, and
The disadvantage is that the operating speed is slow.

By the way, generally when increasing the operating speed, the driving capacity of each element is increased, but increasing the driving capacity increases power consumption. The integration density of semiconductor integrated circuits is rapidly increasing, and there is a demand for semiconductor integrated circuits that can reduce power and delay products.

Purpose of the invention This invention was made in view of the above circumstances.
The purpose is to provide a semiconductor integrated circuit having a buffer circuit with low power consumption and high operating speed.

In other words, in this invention, a capacitor is provided at the gate of a load transistor in an E/E type inverter circuit, this capacitor is charged when the driver transistor is in an on state, and the capacitor is charged when the driver transistor is in an off state. A buffer circuit configured to control conduction of a load transistor using a voltage that is the sum of a charging voltage and a power supply VDII voltage is built into a semiconductor integrated circuit.

Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Figure 3 shows the configuration of the buffer circuit.
An E-type load transistor Q4 and a driver transistor Q are connected in series between a power supply VDD and a ground point GND. Then, the signal IN input terminal and the load transistor Q4
An inverter circuit NOT, a capacitor C, and a first D-type transistor Q are connected in series between the gate of the inverter circuit NOT, the capacitor C, and the first D-type transistor Q.

A second D-type transistor Q for charging the capacitor C is connected between the connection point N1 between the capacitor C and the transistor Q and the power supply VDD, and its gate is connected to the signal IN.
Connect to the input end. An E-type transistor Qs is connected between the gate of the load transistor Q4 and the ground, and its gate is connected to the signal IN input terminal. Also, transistor Q
DI! between the connection point Ns of 4-Ql and the voltage 1lVDD! )
A transistor Q is connected and its gate is connected to a connection point N. Then, a load capacitor CL connected between this connection point N and a ground point GND is driven.

The operation of the configuration 1 as described above will be explained.

In the figure, each transistor is an n-channel type IC/D
It is assumed that it is composed of MO8 transistors, and the electric current is 1 [
It is assumed that VDD is at a high level with respect to ground potential GND.

First, in a steady state where the input signal IN is at H level, the output terminal of the inverter circuit NOT is at low (L) level. At this time, transistors Qv and Qs are connected to the power supply VDD.
, Qa and the current path flowing to the ground point GND, by optimally selecting the dimensions of each element of the transistor Qτ Can be set to ground point GND level. Therefore, at this time, transistor Q is in the off state, Qs is in the on state, and the output O
UT becomes L level. Node N.

A transistor Q is connected to and supplied with the power supply VDD voltage.

If the conduction resistance of the transistor Q is set sufficiently large compared to the transistor Q, the L level of the output signal OUT has almost no effect. At this time, the potential difference between both ends of the capacitor C is approximately the power supply VDD voltage, and positive charges are accumulated at the electrode on the side of the node N, and negative charges are accumulated at the narrow end.

Next, the operation in a transient state where the input signal IN changes from an H level to an L level will be described. At this time, transistors Qy and Q. are turned off. The transistor Qv is a D type, but since the source and drain potentials are approximately at the VDD level, when the gate potential goes to the L level, a substrate bias effect is added, and although it is a D type, it is completely turned off. Then, the output of the inverter circuit NOT begins to rise from the L level to the H level. At this time, the positive voltage accumulated in the node N1 has no discharge path because the transistor Qy=Qs is in the off state, and the inverter circuit NOT
Remove the output. Here, since the transistor Q is of the D type, the potential of the node N increases following the potential of the node N1. Immediately before this transient operation, the potential of node N1 is approximately VDD level, and the potential of node N is G.
Although the voltage is at the ND level, the potentials of the nodes Nl and Nt begin to change toward a level higher than the power supply VDD voltage as a result of the transient change, and eventually rise to approximately twice the power supply VDD voltage. Therefore, transistor Q
4 is in the off state, Q- is in the off state, and the potential of the node N changes from the L level to the H level, and this H level is held by the transistor Q1. At this time, since the load transistor Q4 is controlled to be conductive at a high potential of [2VDtlJ, the following effects can be obtained.

First, as described in the Fi/E buffer circuit shown in Figure 2, the load transistor is E type and its gate voltage is VDD.
Then, the output voltage is r VDD −VYMIJ(ytsu
s rises only up to the threshold voltage of transistor Q4), and when the output voltage reaches near the saturation voltage of the transistor, the voltage of the output transistor Q114! = Since the force decreases rapidly, the output rise time tr also becomes longer. However, in the circuit according to the present invention, since the gate voltage of the 9-load transistor rises to approximately 2 VDD, the output changes quickly, and the output voltage 1'- is approximately at the VDD level.

21. In the circuit according to the present invention, since the load transistor and the driver transistor are of E type, the power supply V
Penetration from DD to ground point GND [fi is only at the time of transient. Therefore, it is a low consumption value flow.

In the above embodiment, an n-channel type MOS transistor has been described, but a p-channel type MOS transistor is also applicable.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention provides a semiconductor integrated circuit having a buffer circuit that consumes less power and can operate at high speed.

[Brief explanation of the drawing]

1 and 2 each show a conventional buffer circuit, and FIG. 3 shows a buffer circuit for a semiconductor integrated circuit according to an embodiment of the present invention. Q4~Q,...transistor, c, ch...capacitor, NO...inverter circuit, VDD...power supply, GND...ground point, IN...input signal, OUT...
...Output signal.

Claims (1)

[Claims] A single-channel MO8 type integrated circuit consisting of enhancement-type and depletion-type transistors, each with an enhancement-type load transistor and a driver transistor connected in series between a power supply and ground, and a capacitor with an input signal supplied thereto. and an inverter circuit that drives the load transistor via a first depletion type transistor, and a photoelectric capacitor connected between a connection point between the capacitor and the first depletion type transistor and a power supply and whose conduction is controlled by an input signal. 1. A semiconductor integrated circuit comprising: a second depletion type transistor for use in the load transistor; and an enhancement type transistor connected between the gate of the load transistor and a ground point and whose conduction is controlled by an input signal.