JPS6041326A - Inverter circuit - Google Patents

Abstract

PURPOSE:To make the operation speed higher and to reduce the power consumption by constituting a CMOS inverter of a P type MOS transistor Tr and an N type MOSTR to use this inverter as a bootstrap type. CONSTITUTION:The first - the third inverter circuits are constituted of N type MOSTRs 2, 4, and 6 as load elements and P type MOSTRs 1, 3, and 5 as driving elements. A prescribed input pulse phiin is inputted to the first and the second inverter circuits, and the first inverter circuit is allowed to fall after the fall of the output of the second inverter circuit. The output of the first inverter is applied to the gate of the TR5 of the third inverter. The output of the second inverter is applied to the gate of the TR6 of the third inverter through an earth potential and a P type MOSTR8. Thus, inverters are used as a bootstrap type to make the operation high-speed and to reduce the power consumption.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a bootstrap type inverter circuit that inverts input pulses at high speed, and particularly relates to an inverter circuit using a P-type MO8+- transistor (MO3T) and an N-type MO8T. .

[Background of the invention]

Conventionally, there are inverters using only N-type MO8Ts and bootstrap type inverters using only P-type MO8Ts.

These are disclosed, for example, in Japanese Unexamined Patent Publication No. 51-35272.

[Purpose of the invention]

The present invention has a speed close to that of using only N-type MO8T,
It is an object of the present invention to provide a CuO2 type bootstrap type inverter which has power consumption close to that of using only P-type MO8T.

[Summary of the invention]

The present invention configures a bootstrap type inverter using a CMOS inverter made up of a PMOS+heran transistor and an NMOS transistor.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows its operating characteristics. This embodiment is a CMOS inverter circuit consisting of P-type MO3TI and N-type MO8T2, P-type MO8T3 and N-type MO8
, T4, and a P-type MO8
It consists of an output inverter circuit consisting of T5, N-type MO8T6, step-down capacitor 7, and P-type MO3T8. P-type MO
8TI, 3.5 sources 1', 3', 5' are positive power supply voltage V. 0, and the sources 2', 4', 6' of the N-type MO8T2°4.6 and the gate 8' of the P-type MO8T8 are fixed to the ground potential. The characteristics of this circuit will be explained below with reference to FIG.

When inputs φ and Iv are input to gates 9 of 1 to 4, 3°4
The potential of the output node 10 of the inverter circuit consisting of
. is V. 0 to the ground potential, and almost at the same time, the potential v1o' at the node 10' also drops.

At this time, the potential of the node 11 decreases slightly because it is connected to the node 10' through the capacitor 7. Thereafter, the output v11 of the inverter node l] composed of nodes 1 and 2 falls with a certain delay relative to 10, so that the inverter delay time is
It is predetermined to be larger than the delay time of the inverter composed of 3 and 4 inverters. This results in 10'
The potential V1o' of is lowered to below the ground potential by 7. Therefore, since a large negative gate voltage is applied to the gate of the P-type MO8T5, a large transfer conductance characteristic is obtained, and the potential of the output 12 is φ. l11 rises at high speed.

FIG. 3 shows another embodiment of the invention. In this embodiment, V is shown in the embodiment waveform diagram of FIG. ’ falling waveform is 104
This eliminates the drawback that the rise speed of the output φ deteriorates due to the delay in the output φ. In this example, P type M
It consists of four inverter circuits consisting of N-type MO8T22゜24.26.28 which form a pair with O8T21, 23゜25.27, respectively, P-type MO3T29.30 and step-down capacitor 31, and operates as shown in Fig. 4. Let's do it. Note that the sources of MO8T21, 23, 25, and 27 are connected to the positive power supply voltage Vcc, respectively, and the sources of MO8T22, 24
, 26, and 28 are fixed at ground potential. The input pulse φ□ causes the potential v3□ of the node 32 of the inverter composed of 21.22 to fall. This potential change brings about a change in the potential VBg of the node 33 through 30, and also changes the potential VBg of the node 34 through the gate capacitance of the P-type MO8T30. is lowered. As a result, the potential ■:14 of the gate 34 becomes lower than the ground potential, so a change in VB2 is quickly transmitted to V3B.

There is no deterioration of the falling characteristic as occurred in FIG. When the potential v3□ of the node 32 falls, the potential Vg4 of the inverter output node 34 composed of 23.degree. 26] is lowered. This potential drop is transmitted to node 33 through node 31, causing the potential V at node 33 to drop below the ground potential as shown in FIG. As a result, the potential φ at the output node 37 rises rapidly, and a high-speed output pulse is obtained.

FIG. 5 shows another embodiment of the invention. In this example, the first
This embodiment has the advantage that the circuit design is easier than the embodiment shown in the figure. This circuit consists of P-type MO3T3, 5.42,
Three inverters each consisting of a pair of N-type MiosT4, 6.43, PMO38, step-down capacitor 7
The gate of 42.43 has an output signal φ. is applied, and one end of the step-down capacitor 7 is connected to the drain of 43. In other words, in Fig. 1, inverter circuits with different delay characteristics must be designed, whereas
In this embodiment, changes in potential at the output terminal 41 are detected 42.43.
node 10 by 7 using an inverter circuit consisting of
Since the voltage is lowered by , there is no need to design the pulse timing for lowering the voltage. However, P type MO3T42 and N
The gate capacitance of type MO3T43 is the output φ. The output load capacity will increase slightly because the load capacity will be 42.4.
(3 channel width constitutes output inverter)
Since it is about 1/4 of MO8T5 and MO8T6, there is little deterioration in the output rise speed due to this.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a CMO3 type boot boot type inverter which has low power consumption and high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing operating characteristics of the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a second embodiment of the invention. FIG. 4 is a diagram showing operating characteristics of the second embodiment of the invention. FIG. 5 is a circuit diagram showing a third embodiment of the present invention. 1.3.5.8...P-type MOS transistor. 2.4.6...N-type MO3+- transistor. Intervention 3 Figure 2 Fang 4- Diagram S episode 6

Claims (1)

[Claims] 1. First to third inverter circuits each having an N-type field-effect transistor as a load element and a first P-type field-effect transistor as a drive element;
．． The second inverter circuits both respond to the rising edge of a predetermined input pulse, and the first inverter circuit falls behind the falling edge of the output of the second inverter circuit. , the output of the first inverter is connected to the first inverter of the third inverter via a capacitive element.
The output of the second inverter circuit is connected to the gate of the P-type field effect transistor of the third inverter via the second
is connected to Boo I- of the P-type field effect transistor of
An inverter circuit that supplies an inverted output of the input pulse from the third inverter circuit.