JPS6430834U - - Google Patents
Info
- Publication number
- JPS6430834U JPS6430834U JP12679787U JP12679787U JPS6430834U JP S6430834 U JPS6430834 U JP S6430834U JP 12679787 U JP12679787 U JP 12679787U JP 12679787 U JP12679787 U JP 12679787U JP S6430834 U JPS6430834 U JP S6430834U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- metal ball
- lead
- semiconductor device
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000000465 moulding Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
Description
第1図は、本考案に係る一実施例を示した平面
図、第2図は、同じく部分断面図である。第3図
は、ハイブリツドICの組立分解斜視図、第4図
は、同じく組立完了斜視図、第5図乃至第7図は
、リードフレーム等を樹脂にて封止する際の各動
作状態での部分断面図、第8図は、樹脂モールド
の際に生じる問題点を図示した部分断面図である
。
1……配線基板、3……素子、5……リードフ
レーム、5b……リード、6……ワイヤ、6a…
…金属球、7……絶縁板、13……溶融樹脂。
FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a partial sectional view of the same. Fig. 3 is an exploded perspective view of the hybrid IC, Fig. 4 is a perspective view of the completed assembly, and Figs. 5 to 7 show the various operating states when sealing the lead frame etc. with resin. FIG. 8 is a partial cross-sectional view illustrating problems that occur during resin molding. DESCRIPTION OF SYMBOLS 1... Wiring board, 3... Element, 5... Lead frame, 5b... Lead, 6... Wire, 6a...
... Metal ball, 7 ... Insulating plate, 13 ... Molten resin.
Claims (1)
の周囲に複数本平行配置したリードの内端とを、
一方のみ金属球を形成してワイヤボンデイングし
、上記素子とリードの内端とを含む主要部を樹脂
にて封止した半導体装置において、 上記金属球を一部又は全部をリード側に配置し
て、ワイヤボンデイングしたことを特徴とする半
導体装置。[Claims for Utility Model Registration] A wiring board on which an element is mounted, and inner ends of a plurality of leads arranged in parallel around the wiring board,
In a semiconductor device in which a metal ball is formed on only one side and wire bonded, and the main part including the element and the inner end of the lead is sealed with resin, the metal ball is partially or completely disposed on the lead side. , a semiconductor device characterized by wire bonding.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12679787U JPH0625959Y2 (en) | 1987-08-19 | 1987-08-19 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12679787U JPH0625959Y2 (en) | 1987-08-19 | 1987-08-19 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6430834U true JPS6430834U (en) | 1989-02-27 |
JPH0625959Y2 JPH0625959Y2 (en) | 1994-07-06 |
Family
ID=31378640
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12679787U Expired - Lifetime JPH0625959Y2 (en) | 1987-08-19 | 1987-08-19 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0625959Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61159746A (en) * | 1985-01-08 | 1986-07-19 | Kyodo Printing Co Ltd | Wire bonding method for ic module |
-
1987
- 1987-08-19 JP JP12679787U patent/JPH0625959Y2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61159746A (en) * | 1985-01-08 | 1986-07-19 | Kyodo Printing Co Ltd | Wire bonding method for ic module |
Also Published As
Publication number | Publication date |
---|---|
JPH0625959Y2 (en) | 1994-07-06 |
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