JPS6425554A - High power circuit board and hybrid integrated circuit thereof - Google Patents

High power circuit board and hybrid integrated circuit thereof

Info

Publication number
JPS6425554A
JPS6425554A JP62182877A JP18287787A JPS6425554A JP S6425554 A JPS6425554 A JP S6425554A JP 62182877 A JP62182877 A JP 62182877A JP 18287787 A JP18287787 A JP 18287787A JP S6425554 A JPS6425554 A JP S6425554A
Authority
JP
Japan
Prior art keywords
foil
aluminum
laminated
layer
metal board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62182877A
Other languages
Japanese (ja)
Other versions
JPH0831546B2 (en
Inventor
Kazuo Kato
Tatsuo Nakano
Shinichiro Asai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP62182877A priority Critical patent/JPH0831546B2/en
Publication of JPS6425554A publication Critical patent/JPS6425554A/en
Publication of JPH0831546B2 publication Critical patent/JPH0831546B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To increase the bonding strength with an insulating layer, to alleviate heat shock between a metal board and a copper foil and to prevent the decrease in withstand voltage of the insulating film, by laminating an aluminum foil, the copper foil and an aluminum foil on the insulating layer on the metal board in this order. CONSTITUTION:An aluminum circuit part 2 for stabilizing withstand voltage is laminated as the lowermost layer on a metal board 6 through an insulating layer 5. A thick copper circuit part 1 is laminated on the part 2 as an intermediate layer. An Al bonding post 3 comprising an Al foil is laminated as an uppermost layer. A soldered outer lead terminal part 4 is provided at the local position of the thick copper circuit. Semiconductors, e.g., a power transistor 7 and a diode 8, are mounted with solder 10. The power transistor 7 and the diode 8 are connected to the aluminum bonding post 3, and a circuit is formed.
JP62182877A 1987-07-22 1987-07-22 High power circuit board and hybrid integrated circuit thereof Expired - Fee Related JPH0831546B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62182877A JPH0831546B2 (en) 1987-07-22 1987-07-22 High power circuit board and hybrid integrated circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62182877A JPH0831546B2 (en) 1987-07-22 1987-07-22 High power circuit board and hybrid integrated circuit thereof

Publications (2)

Publication Number Publication Date
JPS6425554A true JPS6425554A (en) 1989-01-27
JPH0831546B2 JPH0831546B2 (en) 1996-03-27

Family

ID=16125983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62182877A Expired - Fee Related JPH0831546B2 (en) 1987-07-22 1987-07-22 High power circuit board and hybrid integrated circuit thereof

Country Status (1)

Country Link
JP (1) JPH0831546B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002325468A (en) * 2001-04-27 2002-11-08 Matsushita Electric Ind Co Ltd Power converter
JP2010034238A (en) * 2008-07-28 2010-02-12 Shin Kobe Electric Mach Co Ltd Wiring board
US8336202B2 (en) 2005-05-13 2012-12-25 Fuji Electric Co., Ltd. Method of manufacturing a wiring board
JP2015153922A (en) * 2014-02-17 2015-08-24 三菱電機株式会社 power semiconductor device
CN116406090A (en) * 2023-05-15 2023-07-07 台山市科伟电子科技有限公司 Production process of aluminum-based copper-clad aluminum foil plate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002325468A (en) * 2001-04-27 2002-11-08 Matsushita Electric Ind Co Ltd Power converter
US8336202B2 (en) 2005-05-13 2012-12-25 Fuji Electric Co., Ltd. Method of manufacturing a wiring board
JP2010034238A (en) * 2008-07-28 2010-02-12 Shin Kobe Electric Mach Co Ltd Wiring board
JP2015153922A (en) * 2014-02-17 2015-08-24 三菱電機株式会社 power semiconductor device
CN116406090A (en) * 2023-05-15 2023-07-07 台山市科伟电子科技有限公司 Production process of aluminum-based copper-clad aluminum foil plate
CN116406090B (en) * 2023-05-15 2024-02-02 台山市科伟电子科技有限公司 Production process of aluminum-based copper-clad aluminum foil plate

Also Published As

Publication number Publication date
JPH0831546B2 (en) 1996-03-27

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Legal Events

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