JPH0519959Y2 - - Google Patents
Info
- Publication number
- JPH0519959Y2 JPH0519959Y2 JP1986146719U JP14671986U JPH0519959Y2 JP H0519959 Y2 JPH0519959 Y2 JP H0519959Y2 JP 1986146719 U JP1986146719 U JP 1986146719U JP 14671986 U JP14671986 U JP 14671986U JP H0519959 Y2 JPH0519959 Y2 JP H0519959Y2
- Authority
- JP
- Japan
- Prior art keywords
- power chip
- wiring board
- printed wiring
- copper plate
- pwb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 239000007787 solid Substances 0.000 claims description 13
- 230000017525 heat dissipation Effects 0.000 description 8
- 239000004593 Epoxy Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000003566 sealing material Substances 0.000 description 4
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【考案の詳細な説明】
＜産業上の利用分野＞
本考案はパワーチツプ及びデイスクリート部品
混載のソリツド・ステート・リレーに関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a solid state relay that includes a power chip and discrete components.
＜考案の概要＞
本考案は、パワーチツプ及び複数のデイスクリ
ート部品を含むソリツド・ステート・リレーにお
いて、プリント配線板と銅板を備えてなり、該銅
板に前記パワーチツプをダイボンドするととも
に、前記プリント配線板には前記デイスクリート
部品を実装し、前記プリント配線板裏面に前記銅
板を少なくとも一部分を重ねて張り合せて構成
し、プリント配線板の裏面を有効に活用してパツ
ケージの小型化を図り且つ高放熱性を具備させた
ものである。<Summary of the invention> The present invention is a solid state relay including a power chip and a plurality of discrete components, which is equipped with a printed wiring board and a copper plate, the power chip is die-bonded to the copper plate, and the power chip is die-bonded to the printed wiring board. The discrete component is mounted, and at least a portion of the copper plate is laminated on the back side of the printed wiring board, so that the back side of the printed wiring board is effectively utilized to reduce the size of the package and provide high heat dissipation. It is equipped with the following.
＜従来の技術＞
第２図及び第３図に、パワーチツプ及び複数の
デイスクリート部品混載のソリツド・ステート・
リレーの夫々異なる従来例を示す。なお、各図に
おいて、１はパワーチツプ、２は点弧用ホトカブ
ラ、３は受動部品、４はリードピン、５はヒート
スプレツダー、６はアルミ線、７はプリント配線
板（PWB）、８は絶縁封止材料、９はメタルベー
スPWBである。<Prior art> Figures 2 and 3 show a solid-state device that includes a power chip and multiple discrete components.
Different conventional examples of relays are shown. In each figure, 1 is the power chip, 2 is the ignition photocoupler, 3 is the passive component, 4 is the lead pin, 5 is the heat spreader, 6 is the aluminum wire, 7 is the printed wiring board (PWB), and 8 is the insulation. The sealing material 9 is metal base PWB.
第２図のものは、PWB７の材料として、紙フ
エノール、紙エポキシ、ガラスエポキシ等を使用
しており、高放熱性を促進する為にPWBの面積
を広くとり、さらに高熱伝導性絶縁封止材料８に
よる成形後のパツケージ表面積も大きくとつてい
る。また第３図のものは、PWB９の材料として、
セラミツク基板及びメタルベース、ホーロー基板
等の特に基板自体が高放熱性を有するものを使用
している。 The one in Figure 2 uses paper phenol, paper epoxy, glass epoxy, etc. as the material for PWB 7, and has a large PWB area to promote high heat dissipation, and is also made of high thermal conductive insulating sealing material. The surface area of the package after molding according to No. 8 is also large. In addition, the material in Figure 3 is used as the material for PWB9.
A ceramic substrate, a metal base, a hollow substrate, etc., in particular, which have a high heat dissipation property, are used.
＜考案が解決しようとする問題点＞
ところが、前者のパツケージ表面積を大きくし
た構造では、必然的にデバイス形状が大きくな
り、組込機器側から要請される小型化を実現する
ことは困難である。また形状を小さくすること
は、パワー定格の縮小につながり望ましくない。
他方、後者の高放熱性を有するメタルベース
PWB９を使用した場合、前者の一般的PWB７と
異なり、放熱性は優れているが、基板が高価な為
製造コストが高くつくという問題点があつた。<Problems to be solved by the invention> However, with the former structure in which the surface area of the package is increased, the device shape inevitably becomes large, and it is difficult to realize the miniaturization required by the embedded device side. Also, reducing the size is undesirable because it leads to a reduction in power rating.
On the other hand, the latter metal base with high heat dissipation
When PWB9 is used, unlike the former general PWB7, it has excellent heat dissipation, but the problem is that the manufacturing cost is high because the board is expensive.
本考案は、上記事情を鑑みてなされたものであ
り、その目的は、パワーチツプの過渡熱吸収と定
常的熱放散効果をもたせた上で、小型化を実現で
きるソリツド・ステート・リレーを提供すること
にある。 The present invention has been developed in view of the above circumstances, and its purpose is to provide a solid state relay that can realize downsizing while having transient heat absorption and steady heat dissipation effects of the power chip. It is in.
＜問題点を解決するための手段＞
本考案は、パワーチツプ及び複数のデイスクリ
ート部品を含むソリツド・ステート・リレーにお
いて、プリント配線板と銅板を備えてなり、該銅
板に前記パワーチツプをダイボンドするととも
に、前記プリント配線板には前記デイスクリート
部品を実装し、前記プリント配線板裏面に前記銅
板を少なくとも一部分を重ねて張合わせて構成す
るものである。<Means for Solving the Problems> The present invention provides a solid state relay including a power chip and a plurality of discrete components, which comprises a printed wiring board and a copper plate, and the power chip is die-bonded to the copper plate, and The discrete components are mounted on the printed wiring board, and at least a portion of the copper plate is laminated on the back surface of the printed wiring board.
＜作用＞
本考案は上記構成により、パワーチツプをダイ
ボンドした銅板をプリント配線板に張り合せたこ
とにより、パワーチツプの過渡熱吸収及び定常的
放熱効果が得られ且つプリント配線板裏面の有効
活用により容易にパツケージの小形化が図れる。<Function> The present invention has the above-mentioned configuration, and by bonding the copper plate with the power chip die-bonded to the printed wiring board, it is possible to obtain transient heat absorption and constant heat radiation effects of the power chip, and to easily utilize the back side of the printed wiring board. The package can be made smaller.
＜実施例＞
以下、図面の基づき本考案に係るソリツド・ス
テート・リレーの実施例を説明する。<Example> Hereinafter, an example of the solid state relay according to the present invention will be described based on the drawings.
第１図に本考案の一実施例の断面図を示す。同
図において第２図及び第３図に示した従来例の構
成と同一部分には同一の符号を付している。 FIG. 1 shows a sectional view of an embodiment of the present invention. In this figure, the same parts as those of the conventional example shown in FIGS. 2 and 3 are given the same reference numerals.
本実施例のソリツド・ステート・リレーは、パ
ワーチツプ１及び複数のデイスクリート部品２，
３を含むソリツド・ステート・リレーであつて、
プリント配線板（PWB）１０及び該PWB１０と
同程度の面積を有する銅板１１を備えてなり、パ
ワーチツプ１をダイボンドした銅板１１をデイス
クリート部品２，３を実装したPWB１０の裏面
に少なくとも一部分を重ねて張合せて構成され
る。また本実施例において、PWB１０の材料は、
一般に広く用いられている紙フエノール、紙エポ
キシ、ガラスエポキシ等のプリント基板を使用し
ている。 The solid state relay of this embodiment includes a power chip 1, a plurality of discrete components 2,
3, the solid state relay comprising:
It comprises a printed wiring board (PWB) 10 and a copper plate 11 having an area comparable to that of the PWB 10, and the copper plate 11 on which the power chip 1 is die-bonded is overlapped at least partially on the back side of the PWB 10 on which the discrete components 2 and 3 are mounted. It is constructed by joining together. In addition, in this example, the material of the PWB 10 is
Printed circuit boards made of widely used materials such as paper phenol, paper epoxy, and glass epoxy are used.
次に上記構造のソリツド・ステート・リレーの
製造工程を説明する。 Next, the manufacturing process of the solid state relay having the above structure will be explained.
まず銅板１１にパワーチツプ１を高温半田にて
ダイボンドしておき、PWB１０には、点弧用ホ
トカブラー２及びコンデンサ、抵抗等の受動部品
断面図を半田付けしておき、さらにこれら銅板１
１とPWB１０裏面とを半田付けする。なおPWB
１０裏面には、銅パターンが形成されており、且
つ、パワーチツプ１部と重なる部分には予め開口
部がもうけられている。パワーチツプ１とPWB
１０の表面の回路とは、アルミ線６のワイヤーボ
ンデイングにより結線され、外部電極取り出し用
としてリードピン４′が半田にて取りつけられる。
パワーチツプ１のボトム電極は、PWB１０の裏
面パターンから図のごとくＹ型リードピン４′を
通して引き出される。外装成形は高熱伝導性絶縁
封止材料８を使用し、キヤステイング法、デイピ
ング法、ケーシング法等により封止される。 First, the power chip 1 is die-bonded to the copper plate 11 using high-temperature solder, and the ignition photocoupler 2 and cross-sectional diagrams of passive components such as capacitors and resistors are soldered to the PWB 10.
1 and the back side of PWB10. Furthermore, PWB
A copper pattern is formed on the back side of the chip 10, and an opening is previously formed in a portion that overlaps with the power chip 1. Power chip 1 and PWB
The circuit on the surface of 10 is connected by wire bonding using aluminum wire 6, and a lead pin 4' for taking out an external electrode is attached with solder.
The bottom electrode of the power chip 1 is drawn out from the back surface pattern of the PWB 10 through a Y-shaped lead pin 4' as shown in the figure. The exterior molding uses a highly thermally conductive insulating sealing material 8 and is sealed by a casting method, dipping method, casing method, or the like.
上記のような構造とすることで、高価なメタル
ベース基板等の複合基板を適用することなく高放
熱性効果を得ることができ、PWBとして紙フエ
ノール、紙エポキシ、ガラスエポキシ等の一般的
PWBを適用できることによりコスト的に有利で
あり、且つPWB裏面の有効活用により小型化を
図れる。 With the above structure, high heat dissipation effect can be obtained without using a composite board such as an expensive metal base board, and general PWBs such as paper phenol, paper epoxy, glass epoxy, etc.
Applicability of PWB is advantageous in terms of cost, and size reduction can be achieved by effectively utilizing the back side of PWB.
＜考案の効果＞
以上述べてきたように本考案のソリツド・ステ
ート・リレーによれば、極めて簡単な構造で、パ
ワーチツプをダイボンドした銅板をプリント配線
板裏面に張り合せたことにより、パワーチツプの
過渡熱吸収と定常的熱放散効果が得られ且つ容易
に小型化が実現できる。<Effects of the invention> As described above, the solid state relay of the invention has an extremely simple structure, and the power chip die-bonded copper plate is attached to the back of the printed wiring board, thereby reducing the transient heat of the power chip. Absorption and constant heat dissipation effects can be obtained, and miniaturization can be easily achieved.
第１図は本考案のソリツド・ステート・リレー
の一実施例の断面図、第２図及び第３図は夫々異
なる従来のソリツド・ステート・リレーの断面図
である。
１……パワーチツプ、２……点弧用ホトカプ
ラ、３……受動部品、４′……リードピン、６…
…アルミ線、８……絶縁封止材料、１０……プリ
ント配線板（PWB）、１１……銅板。
FIG. 1 is a sectional view of one embodiment of the solid state relay of the present invention, and FIGS. 2 and 3 are sectional views of different conventional solid state relays. 1...Power chip, 2...Ignition photocoupler, 3...Passive components, 4'...Lead pin, 6...
...Aluminum wire, 8...Insulating sealing material, 10...Printed wiring board (PWB), 11...Copper plate.
Claims (1)
含むソリツド・ステート・リレーにおいて、プリ
ント配線板と銅板を備えてなり、該銅板に前記パ
ワーチツプをダイボンドするとともに、前記プリ
ント配線板には前記デイスクリート部品を実装
し、前記プリント配線板裏面に前記銅板を少なく
とも一部分を重ねて張合わせてなることを特徴と
するソリツド・ステート・リレー。 A solid state relay including a power chip and a plurality of discrete components includes a printed wiring board and a copper plate, the power chip is die-bonded to the copper plate, and the discrete components are mounted on the printed wiring board, A solid state relay comprising at least a portion of the copper plate laminated on the back surface of the printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986146719U JPH0519959Y2 (en) | 1986-09-24 | 1986-09-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986146719U JPH0519959Y2 (en) | 1986-09-24 | 1986-09-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6351453U JPS6351453U (en) | 1988-04-07 |
| JPH0519959Y2 true JPH0519959Y2 (en) | 1993-05-25 |
Family
ID=31059444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986146719U Expired - Lifetime JPH0519959Y2 (en) | 1986-09-24 | 1986-09-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0519959Y2 (en) |
-
1986
- 1986-09-24 JP JP1986146719U patent/JPH0519959Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6351453U (en) | 1988-04-07 |
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