JPS6120760Y2 - - Google Patents
Info
- Publication number
- JPS6120760Y2 JPS6120760Y2 JP1980085158U JP8515880U JPS6120760Y2 JP S6120760 Y2 JPS6120760 Y2 JP S6120760Y2 JP 1980085158 U JP1980085158 U JP 1980085158U JP 8515880 U JP8515880 U JP 8515880U JP S6120760 Y2 JPS6120760 Y2 JP S6120760Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead frame
- foil lead
- foil
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 37
- 239000011888 foil Substances 0.000 claims description 22
- 239000000919 ceramic Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 6
- 238000005219 brazing Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
この考案は複数個の外部接続用Al電極を有す
る半導体装置に関し、特に外部接続用Al電極を
取扱い容易な外部リードとして引き出し得る半導
体装置の構造に関するものである。[Detailed Description of the Invention] This invention relates to a semiconductor device having a plurality of Al electrodes for external connection, and particularly to a structure of a semiconductor device in which the Al electrode for external connection can be drawn out as an easy-to-handle external lead.
先ず、この種の従来装置の構造を第１図に示し
説明する。第１図は従来の装置の断面図を示す。
図において、１は複数個の外部接続用Al電極を
有する半導体素子、２はセラミツク基板、３はセ
ラミツク基板２に印刷焼成された厚膜電極、４は
半導体素子１に内蔵困難なコンデンサチツプ、５
は接続用ろう材、６は半導体素子１の外部接続用
Al電極を引き出すボンデイングワイヤ、７は外
部リード、８はヒートシンクを形成し、取付台と
なるマウントプレート、９はセラミツク基板２と
マウントプレート８とを接着する接着剤、１０は
素子を包含するモールド部材である。 First, the structure of this type of conventional device is shown in FIG. 1 and will be explained. FIG. 1 shows a cross-sectional view of a conventional device.
In the figure, 1 is a semiconductor element having a plurality of Al electrodes for external connection, 2 is a ceramic substrate, 3 is a thick film electrode printed and fired on the ceramic substrate 2, 4 is a capacitor chip that is difficult to incorporate into the semiconductor element 1, and 5
6 is a brazing material for connection, and 6 is for external connection of semiconductor element 1.
A bonding wire leading out the Al electrode, 7 an external lead, 8 a mount plate forming a heat sink and serving as a mounting base, 9 an adhesive for bonding the ceramic substrate 2 and the mount plate 8, and 10 a mold member containing the element. It is.
尚、上記ボンデイングワイヤ６及び外部リード
７は半導体素子１の外部接続用Al電極の数だけ
設けられている。 Incidentally, the bonding wires 6 and the external leads 7 are provided in the same number as the external connection Al electrodes of the semiconductor element 1.
次にこのような構成における半導体装置の組立
方法について以下説明する。先ずセラミツク基板
２に印刷焼成された厚膜電極３上に半導体素子１
及びコンデンサチツプ４を乗せ、ろう材５にて接
続する。その後半導体素子１の外部接続用Al電
極をボンデイングワイヤ６により厚膜電極３上に
夫々引き出す。そして外部リード７をろう材５に
て、接続する。次に上記セラミツク基板２を取付
台となるマウントプレート８上に接続剤９により
接着する。そして最後にモールド部材１０により
包含するものである。 Next, a method of assembling a semiconductor device with such a configuration will be described below. First, a semiconductor element 1 is placed on a thick film electrode 3 printed and fired on a ceramic substrate 2.
Then, a capacitor chip 4 is mounted and connected with a brazing material 5. Thereafter, the external connection Al electrodes of the semiconductor element 1 are drawn out onto the thick film electrodes 3 using bonding wires 6, respectively. Then, the external lead 7 is connected using the brazing material 5. Next, the ceramic substrate 2 is bonded onto a mount plate 8, which serves as a mounting base, using a connecting agent 9. Finally, it is covered by the mold member 10.
以上の様な従来装置においては、半導体素子
１、コンデンサチツプ４、及び外部リード７を保
持する為に厚膜電極３を印刷焼成したセラミツク
基板２が用いられておりこのセラミツク基板２が
高価となる。 In the conventional device as described above, a ceramic substrate 2 on which thick film electrodes 3 are printed and fired is used to hold the semiconductor element 1, capacitor chip 4, and external leads 7, and this ceramic substrate 2 is expensive. .
また、半導体素子１の外部接続用Al電極を外
部リード７に引き出す為にボンデイングワイヤ６
とセラミツク基板２に印刷焼成された厚膜電極３
とを介している為に接続箇所が多くそれだけ信頼
性が低かつた。 In addition, bonding wires 6 are used to draw out the external connection Al electrodes of the semiconductor element 1 to the external leads 7.
and a thick film electrode 3 printed and fired on a ceramic substrate 2.
Because it is connected to a large number of connection points, the reliability is low.
さらに、セラミツク基板２がマウントプレート
８に接着剤９により接着されており、半導体素子
１から、マウントプレート８までの熱抵抗が大き
くそれを補なう為に大きなマウントプレート８が
必要となる。又半導体素子１の外部接続用Al電
極をボンデイングワイヤ６で一旦厚膜電極３上に
引き出す為、及び外部リード７を接続する為の接
続パツドが必要となる為、実装効率が悪く、セラ
ミツク基板２が大きくなり、装置全体として大き
なものとなる等の欠点があつた。 Further, since the ceramic substrate 2 is bonded to the mount plate 8 with an adhesive 9, the thermal resistance from the semiconductor element 1 to the mount plate 8 is large, and in order to compensate for this, a large mount plate 8 is required. In addition, since a connecting pad is required to temporarily draw out the externally connected Al electrode of the semiconductor element 1 onto the thick film electrode 3 using the bonding wire 6 and to connect the external lead 7, the mounting efficiency is poor and the ceramic substrate 2 is There were disadvantages such as the large size of the device and the overall size of the device.
この考案は上記のような欠点を解消するためな
されたもので、接続個所が少なく信頼性の高い、
かつ小型の半導体装置を提供するものである。 This idea was made to eliminate the above-mentioned drawbacks, and it has fewer connection points and is highly reliable.
Moreover, a small-sized semiconductor device is provided.
以下、第２図、第３図、第４図および第６図に
示すこの考案の一実施例について説明する。 An embodiment of this invention shown in FIGS. 2, 3, 4, and 6 will be described below.
第２図は本考案に係る半導体装置の断面図、第
３図は上記実施例に於ける外部リードの引き出し
方向が、シングル・イン・ラインの場合の構成部
品図、第４図は上記実施例の斜視図である。 FIG. 2 is a sectional view of the semiconductor device according to the present invention, FIG. 3 is a component diagram in the case where the external lead is pulled out in a single-in-line direction in the above embodiment, and FIG. 4 is a diagram of the above embodiment. FIG.
これら図において、１ａは半導体素子１の外部
接続用Al電極、１７は数百μｍの厚みのAl箔１
７ａを素材として、上記半導体素子１の外部接続
用Al電極１ａへの接続端部１７ｃ以外が第３図
ｂに示されるようにメツキ法等によりCu金属化
１７ｂされ、同一Al箔１７ａでフレーム状に保
持されてなるAl箔リードフレーム、８ａはマウ
ントプレート８に設けられた取付穴である。次に
上記の様に構成されたこの考案の組立方法の一例
について説明する。 In these figures, 1a is an Al electrode for external connection of the semiconductor element 1, and 17 is an Al foil 1 with a thickness of several hundred μm.
7a as a material, parts other than the connection end 17c to the external connection Al electrode 1a of the semiconductor element 1 are coated with Cu metallization 17b by plating method etc. as shown in FIG. 3b, and the same Al foil 17a is made into a frame shape. The aluminum foil lead frame 8a is a mounting hole provided in the mount plate 8. Next, an example of an assembly method of this invention constructed as described above will be explained.
まず、半導体素子１の外部接続用Al電極１ａ
と、Al箔リードフレーム１７の接続端部１７ｃ
とを夫々超音波ボンデイングする次に上記Al箔
リードフレーム１７がボンデイングされた半導体
素子１をマウントプレート８上に乗せ、さらに上
記Al箔リードフレーム１７上にコンデンサチツ
プ４を乗せた状態で熱板、又は炉等を使用してそ
れぞれろう材５によりろう付する。そして最後に
モールド部材１０により包含するものである。 First, the external connection Al electrode 1a of the semiconductor element 1
and the connection end 17c of the Al foil lead frame 17.
Next, the semiconductor element 1 to which the Al foil lead frame 17 is bonded is placed on the mount plate 8, and then the capacitor chip 4 is placed on the Al foil lead frame 17 and placed on a hot plate. Alternatively, each is brazed with a brazing filler metal 5 using a furnace or the like. Finally, it is covered by the mold member 10.
この様に、この考案による装置の場合、高価な
セラミツク基板の必要がなく、また半導体素子１
の外部接続用Al電極１ａを外部に引き出す為に
中断しているものではなく、Al箔リードフレー
ム１７により直接引き出されているので、接続個
所が最少となり信頼性が向上する。さらに半導体
素子１が直接マウントプレート８にろう付されて
いる為、半導体素子１からマウントプレート８ま
での熱抵抗が非常に小さくなりマウントプレート
８を小さくする事が出来る。その上Al箔リード
フレーム１７がCu金属化１７ｂされているの
で、このAl箔リードフレーム１７上に、コンデ
ンサチツプ４の様な他の素子を直接ろう付する事
が可能で、かつAl箔リードフレーム１７が、そ
のまま外部リードとなり得るので、実装効率が高
く、装置全体としてより小さくする事が出来る。
さらにはAl箔リードフレーム１７が柔軟性のあ
る外部リードとなるので、実装時及び装置として
の使用状態に於て、外部リードへのストレスに対
し、装置内部を保護する役目を果す等のすぐれた
効果がある。 In this way, in the case of the device according to this invention, there is no need for an expensive ceramic substrate, and there is no need for an expensive ceramic substrate.
Since the external connection Al electrode 1a is not interrupted in order to be drawn out to the outside, but is drawn out directly by the Al foil lead frame 17, the number of connection points is minimized and reliability is improved. Furthermore, since the semiconductor element 1 is directly brazed to the mount plate 8, the thermal resistance from the semiconductor element 1 to the mount plate 8 is extremely small, allowing the mount plate 8 to be made smaller. Moreover, since the Al foil lead frame 17 is coated with Cu metallization 17b, it is possible to directly braze other elements such as the capacitor chip 4 onto this Al foil lead frame 17, and the Al foil lead frame Since 17 can be used as an external lead as it is, the mounting efficiency is high and the device as a whole can be made smaller.
Furthermore, since the Al foil lead frame 17 serves as a flexible external lead, it has excellent properties such as protecting the inside of the device against stress on the external lead during mounting and when the device is in use. effective.
第６図は外部リードの引き出し方向がデユア
ル・イン・ラインの場合の構成部品図を示し、効
果については前記この考案の一実施例の場合と同
様の効果があるものである。 FIG. 6 shows a diagram of the components when the external lead is pulled out in a dual-in-line direction, and the effect is similar to that of the embodiment of this invention described above.
このようにこの考案においては信頼性の高い、
すぐれた装置を得る事が出来、さらには、よりコ
ンパクトで安価な装置を得る事が出来るものであ
る。 In this way, this idea has high reliability,
An excellent device can be obtained, and furthermore, a more compact and inexpensive device can be obtained.
そして、この考案は放熱を要する大電力用集積
半導体素子と特に該集積半導体素子に内蔵困難な
素子を含む装置の場合にその効果がある。 This invention is effective for high power integrated semiconductor devices that require heat dissipation, and especially for devices that include elements that are difficult to incorporate into the integrated semiconductor device.
第５図はこの考案の他の実施例を示す断面図で
あり、第２図と異なる点は第２図に示される如く
モールド部材１０で全体を包含する代りにプリコ
ート材１１で要所のみを覆つた点でその作用効果
は上述と同様である。 FIG. 5 is a sectional view showing another embodiment of this invention, and the difference from FIG. 2 is that instead of covering the entire body with the mold member 10 as shown in FIG. The effect is the same as described above in that it is covered.
なお、以上はAl箔リードフレームの両面をCu
金属化したものについて述べたが片面のみとして
も良く、また半導体素子の外部接続用電極を数10
μｍ突起させても良い。 In addition, in the above, both sides of the Al foil lead frame are
Although we have talked about metallized ones, it is also possible to use only one side, and several dozen electrodes for external connection of semiconductor elements can be used.
It is also possible to protrude by μm.
以上のようにこの考案によれば、半導体素子の
外部接続用Al電極をAl箔リードフレームにより
直接引き出しているので、接続個所が少なく信頼
性が高く、また上記Al箔リードフレームをCu金
属化しているので、Al箔リードフレーム上にコ
ンデンサチツプ等の素子を直接ろう付することが
でき実装効率が高く小型化が可能となる等効果が
ある。 As described above, according to this invention, since the Al electrode for external connection of the semiconductor element is directly drawn out through the Al foil lead frame, there are few connection points and high reliability is achieved. This makes it possible to directly braze elements such as capacitor chips onto the Al foil lead frame, resulting in high mounting efficiency and miniaturization.
第１図は従来の半導体装置を示す断面図、第２
図および第４図はこの考案の一実施例を示す断面
図、第３図は第２図に示される半導体装置の各構
成部品を示す斜視図、第５図および第６図はこの
考案の他の実施例を示す断面図およびその各構成
部品を示す斜視図である。
図において、１は半導体素子、５はろう材、８
はマウントプレート、１０はモールド部材、１７
はAl箔リードフレームである。なお、図中同一
符号は同一または相当部分を示す。
Figure 1 is a sectional view showing a conventional semiconductor device, Figure 2 is a cross-sectional view showing a conventional semiconductor device;
4 and 4 are cross-sectional views showing one embodiment of this invention, FIG. 3 is a perspective view showing each component of the semiconductor device shown in FIG. 2, and FIGS. FIG. 2 is a cross-sectional view showing an embodiment of the present invention and a perspective view showing each component thereof. In the figure, 1 is a semiconductor element, 5 is a brazing material, and 8 is a semiconductor element.
is a mount plate, 10 is a mold member, 17
is an Al foil lead frame. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
素子と、前記半導体素子を支持するとともに該
半導体素子の発生熱を吸収し、放熱するマウン
トプレートと、前記複数個の外部接続用Al電
極にそれぞれ接続されたAl箔リードフレーム
と、前記半導体素子、前記マウントプレート及
び前記Al箔リードフレームを包含するモール
ド部材とを備え、前記Al箔リードフレームの
うち前記外部接続用Al電極との接続部を除
き、該Al箔リードフレームの表面をCu金属化
し、該Cu金属化されたAl箔リードフレームを
外部リードとするとともに、該Cu金属化され
たAl箔リードフレーム上に受動素子又は半導
体素子をマウントしたことを特徴とする半導体
装置。 (2) Al箔リードは、厚みが数100umである実用新
案登録請求の範囲第１項記載の半導体装置。[Utility Model Claims] (1) A semiconductor device comprising: a semiconductor element having a plurality of Al electrodes for external connection, a mount plate supporting the semiconductor element and absorbing and dissipating heat generated by the semiconductor element, an Al foil lead frame connected to each of the plurality of Al electrodes for external connection, and a molded member containing the semiconductor element, the mount plate, and the Al foil lead frame, wherein the surface of the Al foil lead frame except for the connection portion with the Al electrodes for external connection of the Al foil lead frame is Cu metallized, the Cu metallized Al foil lead frame is used as an external lead, and a passive element or a semiconductor element is mounted on the Cu metallized Al foil lead frame. (2) A semiconductor device according to Utility Model Claim 1, wherein the Al foil lead has a thickness of several hundreds of microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980085158U JPS6120760Y2 (en) | 1980-06-17 | 1980-06-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1980085158U JPS6120760Y2 (en) | 1980-06-17 | 1980-06-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS578756U JPS578756U (en) | 1982-01-18 |
| JPS6120760Y2 true JPS6120760Y2 (en) | 1986-06-21 |
Family
ID=29447427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1980085158U Expired JPS6120760Y2 (en) | 1980-06-17 | 1980-06-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6120760Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022277Y2 (en) * | 1985-03-29 | 1990-01-19 | ||
| JP4661645B2 (en) | 2005-03-23 | 2011-03-30 | トヨタ自動車株式会社 | Power semiconductor module |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52117551A (en) * | 1976-03-29 | 1977-10-03 | Mitsubishi Electric Corp | Semiconductor device |
-
1980
- 1980-06-17 JP JP1980085158U patent/JPS6120760Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52117551A (en) * | 1976-03-29 | 1977-10-03 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS578756U (en) | 1982-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2592308B2 (en) | Semiconductor package and computer using the same | |
| JPS6370498A (en) | Combination of ceramic substrate and radiator | |
| US6351389B1 (en) | Device and method for packaging an electronic device | |
| JPS6146061B2 (en) | ||
| JPS6120760Y2 (en) | ||
| JPH08107166A (en) | Heat dissipating fin | |
| JPH0773122B2 (en) | Sealed semiconductor device | |
| JP2620611B2 (en) | Substrate for mounting electronic components | |
| JPH0669119B2 (en) | Heat dissipation device for electronic components | |
| JPS6112678Y2 (en) | ||
| JPH08148647A (en) | Semiconductor device | |
| JPS6125247Y2 (en) | ||
| JP3295987B2 (en) | Method for manufacturing semiconductor device | |
| JPS6125248Y2 (en) | ||
| JPS6220701B2 (en) | ||
| JPH0574985A (en) | Semiconductor element mounting structure | |
| JPS6120757Y2 (en) | ||
| JP3238906B2 (en) | Semiconductor device | |
| JP3127149B2 (en) | Semiconductor device | |
| JPS60200545A (en) | Mounting substrate | |
| JP3206545B2 (en) | Stackable semiconductor device and module | |
| JP2736155B2 (en) | Hybrid module circuit device | |
| KR900001744B1 (en) | Semiconductor device | |
| JP2671424B2 (en) | Semiconductor device | |
| JP3036484B2 (en) | Semiconductor device and manufacturing method thereof |