JPS6112678Y2 - - Google Patents

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Publication number
JPS6112678Y2
JPS6112678Y2 JP1980139942U JP13994280U JPS6112678Y2 JP S6112678 Y2 JPS6112678 Y2 JP S6112678Y2 JP 1980139942 U JP1980139942 U JP 1980139942U JP 13994280 U JP13994280 U JP 13994280U JP S6112678 Y2 JPS6112678 Y2 JP S6112678Y2
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JP
Japan
Prior art keywords
semiconductor element
foil
electrode
external connection
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1980139942U
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Japanese (ja)
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JPS5764165U (en
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Priority to JP1980139942U priority Critical patent/JPS6112678Y2/ja
Publication of JPS5764165U publication Critical patent/JPS5764165U/ja
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Publication of JPS6112678Y2 publication Critical patent/JPS6112678Y2/ja
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 この考案は複数個の外部接続用Al電極を有す
る半導体素子に於て、その外部接続用Al電極を
取扱い容易な外部リードとして引き出し得る半導
体装置の構造に関するものである。[Detailed Description of the Invention] This invention relates to the structure of a semiconductor device in which, in a semiconductor element having a plurality of external connection Al electrodes, the external connection Al electrodes can be drawn out as easily handled external leads.

先ず、この種の従来装置の構造を第１図に示し
説明する。第１図は従来装置の断面図を示す。 First, the structure of this type of conventional device is shown in FIG. 1 and will be explained. FIG. 1 shows a sectional view of a conventional device.

図に於て、１は複数個の外部接続用Al電極を
有する半導体素子、２はセラミツク基板、３はセ
ラミツク基板２に印刷焼成された厚膜電極、４は
半導体素子１に内蔵困難なコンデンサチツプ、５
は接続用ろう材、６は半導体素子１の外部接続用
Al電極を引き出すボンデイングワイヤ、７は外
部リード、８はヒートシンクを形成し取付台とな
るマウントプレート、９はセラミツク基板２とマ
ウントプレート８とを接着する接着剤、１０は素
子を囲包するモールド部材である。尚、上記ボン
デイングワイヤ６、及び外部リード７のそれぞれ
の数は、半導体素子１の外部接続用Al電極の数
だけあるわけである。 In the figure, 1 is a semiconductor element having multiple Al electrodes for external connection, 2 is a ceramic substrate, 3 is a thick film electrode printed and fired on the ceramic substrate 2, and 4 is a capacitor chip that is difficult to incorporate into the semiconductor element 1. ,5
6 is a brazing material for connection, and 6 is for external connection of semiconductor element 1.
A bonding wire for drawing out the Al electrode, 7 is an external lead, 8 is a mount plate that forms a heat sink and serves as a mounting base, 9 is an adhesive for bonding the ceramic substrate 2 and the mount plate 8, and 10 is a mold member that surrounds the element. It is. Note that the number of bonding wires 6 and external leads 7 is equal to the number of external connection Al electrodes of semiconductor element 1.

次に、この様に構成された従来装置の組立方法
について説明する。 Next, a method of assembling the conventional device configured in this manner will be explained.

まず、セラミツク基板２に印刷焼成された厚膜
電極３上に、半導体素子１及びコンデンサチツプ
４を乗せろう材５にて接続する。その後半導体素
子１の外部接続用Al電極をボンデインワイヤ６
により厚膜電極３上に夫々引き出す。そして外部
リード７をろう材５にて接続する。次に上記セラ
ミツク基板５を取付台となるマウントプレート８
上に接着剤９により接着する。そして最後にモー
ルド部材１０により囲包するものである。 First, a semiconductor element 1 and a capacitor chip 4 are placed on a thick film electrode 3 printed and fired on a ceramic substrate 2 and connected using a brazing material 5. After that, the aluminum electrode for external connection of the semiconductor element 1 is connected to the bond wire 6.
are drawn out onto the thick film electrode 3 respectively. Then, the external lead 7 is connected with the brazing material 5. Next, a mount plate 8 serves as a mounting base for the ceramic substrate 5.
It is adhered to the top using adhesive 9. Finally, it is surrounded by a mold member 10.

以上の様な従来装置に於ては、半導体素子１、
コンデンサチツプ４及び外部リード７を保持する
為に、厚膜電極３を印刷焼成したセラミツク基板
２が用いられており、このセラミツク基板２が高
価となる。 In the conventional device as described above, the semiconductor element 1,
In order to hold the capacitor chip 4 and the external leads 7, a ceramic substrate 2 on which thick film electrodes 3 are printed and fired is used, and this ceramic substrate 2 is expensive.

また、半導体素子１の外部接続用Al電極を外
部リード７に引き出す為に、ボンデイングワイヤ
６とセラミツク基板２に印刷焼成された厚膜電極
３とを介している為、接続箇所が多くなりそれだ
け信頼性も低いものとなつていた。 In addition, in order to lead out the external connection Al electrode of the semiconductor element 1 to the external lead 7, the bonding wire 6 and the thick film electrode 3 printed and fired on the ceramic substrate 2 are used, which increases the number of connection points and increases the reliability. Sexuality also became low.

さらにセラミツク基板２が、マウントプレート
８に接着剤９により接着されており、半導体素子
１からマウントプレート８までの熱抵抗が大きく
なる。それを補う為に大きなマウントプレート８
が必要となる。又、半導体素子１の外部接続用
Al電極をボンデイングワイヤ６で一旦厚膜電極
３上に引き出す為に及び外部リード７を接続する
為の接続パツドが必要となる為に、実装効率が悪
く、セラミツク基板２が大きくなり装置全体とし
て大きなものとなる等の欠点があつた。 Furthermore, the ceramic substrate 2 is bonded to the mount plate 8 with an adhesive 9, which increases the thermal resistance from the semiconductor element 1 to the mount plate 8. To compensate for this, a large mount plate 8
Is required. Also, for external connection of semiconductor element 1
Since a connection pad is required to pull out the Al electrode onto the thick film electrode 3 using the bonding wire 6 and to connect the external lead 7, the mounting efficiency is poor and the ceramic substrate 2 is large, making the entire device large. There were disadvantages such as becoming a thing.

この考案は、上記従来装置のもつ種々の欠点を
除去するためになされたもので、すぐれた半導体
装置の構造を提供するものである。 This invention was made to eliminate various drawbacks of the above-mentioned conventional devices, and provides an excellent semiconductor device structure.

以下、第２図、第３図、第４図、第５図、第６
図に示すこの考案の一実施例について説明する。 Below, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6
An embodiment of this invention shown in the figure will be described.

第２図はこの考案の一実施例を示す半導体装置
の断面図、第３図は上記実施例に於ける外部リー
ドの引出し方向がシングルインラインの場合の構
成部品の展開斜視図、第４図は上記実施例に於け
るボンデイング前の半導体素子部の拡大断面図、
第５図は上記実施例に於けるボンデイング後の半
導体素子部の拡大断面図、第６図は、上記実施例
の組立后の斜視図を示し、４個の外部接続用Al
電極を有する半導体素子の場合について例示す
る。 FIG. 2 is a sectional view of a semiconductor device showing an embodiment of this invention, FIG. 3 is an exploded perspective view of the components in the case where the external leads are drawn out in a single in-line direction in the above embodiment, and FIG. An enlarged sectional view of the semiconductor element part before bonding in the above embodiment,
FIG. 5 is an enlarged sectional view of the semiconductor element part after bonding in the above embodiment, and FIG. 6 is a perspective view of the above embodiment after assembly, showing the four external connection Al
The case of a semiconductor element having electrodes will be exemplified.

図に於て、１ａは半導体素子１の外部接続用
Al電極。１１は耐熱性、両面接着性及び柔軟性
を有する絶縁シートで、１１ａは半導体素子１が
通る様に絶縁シート１１にあけられた窓穴。１７
は数10μｍ〜数100μｍの厚みのAl箔１７ａを素
材として上記半導体素子１の外部接続用Al電極
１ａへの接続端部１７ｃ以外がメツキ法等により
Cu金属化１７ｂされ同一Al箔１７ａでフレーム
状に保持されてなるAl箔リードフレーム。８ａ
はマウントプレートに設けられた取付穴で、８ｂ
は半導体素子１を収納する凹部、８ｃは該凹部８
ｂ内に設けられた半導体素子１の位置決め用凹
部、Ａはボンデイング用のツール。Ｂはボンデイ
ング後の半導体素子１のエツジ部とAl箔リード
との間〓。である。 In the figure, 1a is for external connection of semiconductor element 1.
Al electrode. Reference numeral 11 denotes an insulating sheet having heat resistance, double-sided adhesiveness, and flexibility, and 11a a window hole made in the insulating sheet 11 so that the semiconductor element 1 can pass through. 17
Using an Al foil 17a having a thickness of several tens of μm to several hundreds of μm as a material, the parts other than the connection end 17c to the external connection Al electrode 1a of the semiconductor element 1 are plated by a plating method or the like.
An Al foil lead frame made of Cu metallized 17b and held in a frame shape by the same Al foil 17a. 8a
is the mounting hole provided on the mount plate, 8b
8c is a recessed portion for housing the semiconductor element 1, and 8c is the recessed portion 8.
A is a recess for positioning the semiconductor element 1 provided in b, and A is a bonding tool. B is between the edge part of the semiconductor element 1 after bonding and the Al foil lead. It is.

次に上記の様に構成されたこの考案の組立方法
の一実施例について説明する。 Next, an embodiment of the assembly method of this invention constructed as described above will be described.

まず、半導体素子１をマウントプレート８の半
導体素子収納凹部８ｂに設けられた半導体素子位
置決め用凹部８ｃに乗せ、その後、絶縁シート１
１をマウントプレート８上に貼り、その絶縁シー
ト１１上にAl箔リードフレーム１７を乗せる。
さらに、Al箔リードフレーム１７上にコンデン
サチツプ４を乗せた状態で、熱板、又は炉等を使
用して、半導体素子１、コンデンサチツプ４のそ
れぞれをろう材５によりろう付する。それから
後、ボンデイング用のツールＡにより半導体素子
１の外部接続用Al電極１ａと、Al箔リードフレ
ーム１７の接続端部１７ｃとを夫々、超音波ボン
デイング方法によりボンデイングする。この場
合、第４図に示す様にボンデイング用ツールＡ
は、すべてのAl箔リードフレームの接続端部１
７ｃを同時にボンデイングする構造のものでも良
いし、又、各接続端部１７ｃを別々にボンデイン
グする構造のものでも良い。そして最後にモール
ド部材１０により囲包するものである。 First, the semiconductor element 1 is placed on the semiconductor element positioning recess 8c provided in the semiconductor element storage recess 8b of the mount plate 8, and then the insulating sheet 1
1 on the mount plate 8, and the Al foil lead frame 17 is placed on the insulating sheet 11.
Further, with the capacitor chip 4 placed on the Al foil lead frame 17, the semiconductor element 1 and the capacitor chip 4 are each brazed with the brazing material 5 using a hot plate, a furnace, or the like. After that, the bonding tool A is used to bond the external connection Al electrode 1a of the semiconductor element 1 and the connection end 17c of the Al foil lead frame 17, respectively, by an ultrasonic bonding method. In this case, as shown in Fig. 4, the bonding tool A
Connecting end 1 of all Al foil lead frames
7c may be bonded at the same time, or each connection end 17c may be bonded separately. Finally, it is surrounded by a mold member 10.

この様に、この考案による半導体装置の場合に
は、高価なセラミツク基板の必要がなく、また半
導体素子１の外部接続用Al電極１ａを外部に引
き出す為に、中継しているものがなく、Al箔リ
ードフレーム１７のみにより直接引き出されるの
で、接続箇所が最少となり信頼性が向上する。さ
らに半導体素子１が直接マウントプレート８にろ
う付されている為に、半導体素子１からマウント
プレート８までの熱抵抗が非常に小さくなり、マ
ウントプレート８を小さくする事が出来る。その
上Al箔リードフレーム１７がCu金属化１７ｂさ
れているので、このAl箔リードフレーム１７上
に、コンデンサチツプ４の様な他の素子を直接ろ
付する事が可能で、かつAl箔リードフレーム１
７が、そのまま外部リードとなり得るので、実装
効率が高く、装置全体としてより小さくする事が
出来る。さらにはAl箔リードフレーム１７が柔
軟性のある外部リードとなるので、実装時及び装
置としての使用状態に於て、外部リードへのスト
レスに対し装置内部を保護する役目を果す。 In this way, in the case of the semiconductor device according to this invention, there is no need for an expensive ceramic substrate, and there is no need for a relay to bring out the external connection Al electrode 1a of the semiconductor element 1 to the outside. Since it is directly pulled out only by the foil lead frame 17, the number of connection points is minimized and reliability is improved. Furthermore, since the semiconductor element 1 is directly brazed to the mount plate 8, the thermal resistance from the semiconductor element 1 to the mount plate 8 becomes extremely small, and the mount plate 8 can be made smaller. Furthermore, since the Al foil lead frame 17 is coated with Cu metallization 17b, it is possible to directly attach other elements such as the capacitor chip 4 onto the Al foil lead frame 17. 1
Since 7 can be used as an external lead as it is, the mounting efficiency is high and the device as a whole can be made smaller. Furthermore, since the Al foil lead frame 17 serves as a flexible external lead, it serves to protect the inside of the device against stress on the external leads during mounting and when the device is in use.

また、半導体素子１がマウントプレート８に設
けられて半導体素子収納凹部８ｂに収納されてお
り、Al箔リードフレーム１７の接続端部１７ｃ
が突起していないので半導体素子１及び接続端部
１７ｃを外力から保護する事が出来る。 Further, the semiconductor device 1 is provided on the mount plate 8 and is housed in the semiconductor device storage recess 8b, and the connection end 17c of the Al foil lead frame 17 is mounted on the semiconductor device 1.
Since there is no protrusion, the semiconductor element 1 and the connecting end 17c can be protected from external force.

その上、半導体素子１のエツジ部とAl箔リー
ドとの間〓Ｂは十分に得られ、エツジ部でシヨー
トする事はない等の種々のすぐれた効果がある。 In addition, there are various excellent effects such as sufficient 〓B between the edge portion of the semiconductor element 1 and the Al foil lead, and no shot at the edge portion.

第７図はこの考案による他の実施例の断面図を
示し、図に於いて、モールド部材１０で囲包する
代りに、プリコート材１２で要所のみを覆うもの
である。効果については、前記この考案の一実施
例の場合と同等の効果があるものである。 FIG. 7 shows a cross-sectional view of another embodiment of this invention, in which only important parts are covered with a precoat material 12 instead of being surrounded by a mold member 10. As for the effect, it has the same effect as the one embodiment of this invention described above.

以上の様に、この考案によれば信頼性に於いて
すぐれた装置を得る事が出来、さらにはよりコン
パクトで安価な装置を得る事が出来るものであ
る。そして、この考案は放熱を要する大電力用半
導体素子、特に、該半導体素子に内蔵困難な素子
を含む装置の場合にその効果が大きいものであ
る。 As described above, according to this invention, it is possible to obtain a device with excellent reliability, and furthermore, it is possible to obtain a device that is more compact and inexpensive. This invention is highly effective for high-power semiconductor devices that require heat dissipation, particularly for devices that include elements that are difficult to incorporate into the semiconductor device.

尚、この考案の場合、必要に応じて半導体素子
１の外部接続用Al電極１ａを数10μｍに突起さ
せた場合も可能で同様の効果があるものである。 In the case of this invention, it is also possible to make the external connection Al electrode 1a of the semiconductor element 1 protrude several tens of micrometers, if necessary, and the same effect can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の断面図、第２図は
この考案の一実施例を示す半導体装置の断面図、
第３図はその構成部品の展開斜視図、第４図はこ
の考案の実施例に於けるボンデイング前の半導体
素子部の拡大断面図、第５図はボンデイング後の
半導体素子部の拡大断面図、第６図はこの考案の
ものの組立后の斜視図、第７図はこの考案の他の
実施例を示す断面図を示す。 図中、１……半導体素子、２……セラミツク基
板、３……厚膜電極、４……コンデンサチツプ、
５……ろう材、６……ボンデイングワイヤ、７…
…外部リード、８……マウントプレート、９……
接着剤、１０……モールド部材、１ａ……半導体
素子の外部接続用Al電極、１１……絶縁シート
で１１ａ……窓穴、１７……Al箔リードフレー
ム、１７ａ……その素材となるAl箔、１７ｂ…
…Cu金属化部、１７ｃ……半導体素子への接続
端部、８ａ……取付穴、８ｂ……半導体素子収納
凹部、８ｃ……半導体素子位置決め用凹部、Ａ…
…ボンデイング用ツール、Ｂ……半導体素子のエ
ツジ部とAl箔リードとの間〓、１２……プリコ
ート材を示す。尚、図中、同一符号は同一又は相
当部分を示す。 FIG. 1 is a sectional view of a conventional semiconductor device, and FIG. 2 is a sectional view of a semiconductor device showing an embodiment of this invention.
3 is an exploded perspective view of its constituent parts, FIG. 4 is an enlarged sectional view of the semiconductor element portion before bonding in an embodiment of this invention, and FIG. 5 is an enlarged sectional view of the semiconductor element portion after bonding. FIG. 6 is a perspective view of this invention after assembly, and FIG. 7 is a sectional view showing another embodiment of this invention. In the figure, 1... semiconductor element, 2... ceramic substrate, 3... thick film electrode, 4... capacitor chip,
5... Brazing metal, 6... Bonding wire, 7...
...External lead, 8...Mount plate, 9...
Adhesive, 10...Mold member, 1a...Al electrode for external connection of the semiconductor element, 11...Insulating sheet 11a...Window hole, 17...Al foil lead frame, 17a...Al foil as its material , 17b...
...Cu metallized portion, 17c...Connection end to semiconductor element, 8a...Mounting hole, 8b...Semiconductor element storage recess, 8c...Semiconductor element positioning recess, A...
. . . Bonding tool, B . . . Between the edge portion of the semiconductor element and the Al foil lead, 12 . . . Precoat material is shown. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】 (1) 複数個の外部接続用Al電極もしくは数10μ
ｍに突起させたAl電極を有する半導体素子、
この半導体素子を収納する凹部及び上記半導体
素子の位置決め用凹部を有し、ヒートシンクを
形成し、取付台となるマウントプレート、一端
が上記半導体素子のAl電極と夫々接続される
複数個のAl箔リードが同一Al箔でフレーム状
に保持されてなるAl箔リードフレーム、 上記マウントプレートに上記Al箔リードフ
レームを絶縁保持する絶縁シート、上記半導体
素子を囲包するモールド部材とで構成され、上
記Al箔リードフレームに於て、上記半導体素
子の外部接続用Al電極への接続端部以外の片
面（もしくは両面）がCu金属化されてなり、
Cu金属化されていない一端が半導体素子の外
部接続用Al電極と接続されてなる半導体装
置。 (2) Al箔リードフレームの厚みが数10μｍ〜数
100μｍの厚みからなる実用新案登録請求の範
囲第１項記載の半導体装置。 (3) 絶縁シートが、耐熱性、両面接着性及び柔軟
性を有してなる実用新案登録請求の範囲第１項
および第２項のいずれかに記載の半導体装置。 (4) Cu金属化された上記Al箔リード上に、上記
半導体素子とは別の半導体素子、又は受動素子
をマウントしてなる実用新案登録請求の範囲第
１項、第２項および第３項のいずれかに記載の
半導体装置。 (5) 半導体素子の外部接続用Al電極がCu金属化
された上記Al箔リードにより引き出され、該
Al箔リードが同時に外部リードとしてなる実
用新案登録請求の範囲第１項、第２項、第３項
および第４項のいずれかに記載の半導体装置。[Claims for Utility Model Registration] (1) Multiple Al electrodes for external connection or several tens of μm
a semiconductor element having an Al electrode protruding into m;
A mount plate having a recess for housing the semiconductor element and a recess for positioning the semiconductor element, forming a heat sink and serving as a mounting base, and a plurality of Al foil leads each having one end connected to an Al electrode of the semiconductor element. The aluminum foil lead frame is made of the same Al foil and is held in a frame shape, an insulating sheet that insulates and holds the Al foil lead frame on the mount plate, and a mold member that surrounds the semiconductor element, and the aluminum foil In the lead frame, one side (or both sides) of the semiconductor element other than the connection end to the external connection Al electrode is metallized with Cu,
A semiconductor device in which one end that is not Cu-metalized is connected to an Al electrode for external connection of a semiconductor element. (2) The thickness of the Al foil lead frame is several tens of μm to several
The semiconductor device according to claim 1, which has a thickness of 100 μm. (3) The semiconductor device according to any one of claims 1 and 2, wherein the insulating sheet has heat resistance, double-sided adhesiveness, and flexibility. (4) Scope of Utility Model Registration Claims 1, 2 and 3, in which a semiconductor element other than the semiconductor element or a passive element is mounted on the Al foil lead metallized with Cu. The semiconductor device according to any one of the above. (5) The Al electrode for external connection of the semiconductor element is drawn out by the above-mentioned Cu metalized Al foil lead, and the
A semiconductor device according to any one of claims 1, 2, 3, and 4, wherein the Al foil lead simultaneously serves as an external lead.
JP1980139942U 1980-09-30 1980-09-30 Expired JPS6112678Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980139942U JPS6112678Y2 (en) 1980-09-30 1980-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980139942U JPS6112678Y2 (en) 1980-09-30 1980-09-30

Publications (2)

Publication Number Publication Date
JPS5764165U JPS5764165U (en) 1982-04-16
JPS6112678Y2 true JPS6112678Y2 (en) 1986-04-19

Family

ID=29499873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980139942U Expired JPS6112678Y2 (en) 1980-09-30 1980-09-30

Country Status (1)

Country Link
JP (1) JPS6112678Y2 (en)

Also Published As

Publication number Publication date
JPS5764165U (en) 1982-04-16

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