JPH0331092Y2 - - Google Patents
Info
- Publication number
- JPH0331092Y2 JPH0331092Y2 JP1985130097U JP13009785U JPH0331092Y2 JP H0331092 Y2 JPH0331092 Y2 JP H0331092Y2 JP 1985130097 U JP1985130097 U JP 1985130097U JP 13009785 U JP13009785 U JP 13009785U JP H0331092 Y2 JPH0331092 Y2 JP H0331092Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit element
- printed wiring
- wiring board
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 4
- 230000020169 heat generation Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000006071 cream Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【考案の詳細な説明】
（産業上の利用分野）
本考案は、集積回路素子取付機構に関するもの
であり、詳しくは、リードレスチツプキヤリア
（LCC）構造の集積回路素子の取付機構に関する
ものである。[Detailed description of the invention] (Industrial application field) The present invention relates to an integrated circuit device mounting mechanism, and more specifically, to a mounting mechanism for an integrated circuit device having a leadless chip carrier (LCC) structure. .
（従来の技術）
集積回路素子１０の一種に、第４図に示すよう
に、一方の面１１から側面１２にかけて複数の接
続パターン１３が形成され他方の面１４には絶縁
部材１５が設けられたリードレスチツプキヤリア
（LCC）構造のものがある。(Prior Art) As shown in FIG. 4, a type of integrated circuit element 10 has a plurality of connection patterns 13 formed from one surface 11 to a side surface 12, and an insulating member 15 provided on the other surface 14. Some have a leadless chip carrier (LCC) structure.
従来、このような集積回路素子１０をプリント
配線板２０に取り付けるのにあたつては、例えば
第５図に示すように、プリント配線板２０に集積
回路素子１０の一方の面１１に形成されている複
数の接続パターン１３に対応した複数の配線パタ
ーン２１を形成しておき、これら所定の接続パタ
ーン１３と配線パターン２１を重ね合わせて例え
ばクリームはんだなどによりはんだ付けにより接
続することが行われていた。 Conventionally, when attaching such an integrated circuit element 10 to a printed wiring board 20, for example, as shown in FIG. A plurality of wiring patterns 21 corresponding to a plurality of connection patterns 13 are formed in advance, and these predetermined connection patterns 13 and wiring patterns 21 are overlapped and connected by soldering, for example, with cream solder. .
ところで、このようにして取り付けられた集積
回路素子１０の放熱に着目すると、絶縁部材１５
の表面からの自然放熱やプリント配線板２０を介
しての放熱が考えられる。 By the way, when paying attention to the heat dissipation of the integrated circuit element 10 attached in this way, it is found that the insulating member 15
Natural heat radiation from the surface or heat radiation via the printed wiring board 20 can be considered.
（考案が解決ようとする問題点）
しかし、これらの放熱効果は十分ではなく、集
積回路素子１０の発熱が比較的大きい場合には、
発熱による集積回路素子１０自体の温度上昇に対
する対策を別途講じる必要がある。(Problems to be solved by the invention) However, these heat dissipation effects are not sufficient, and when the heat generation of the integrated circuit element 10 is relatively large,
It is necessary to take additional measures against the temperature rise of the integrated circuit element 10 itself due to heat generation.
また、このような構造によれば、集積回路素子
１０がプリント配線板２０の表面から少なくとも
その厚さ分だけ突出することになり、プリント配
線板１０を含む機構を薄くしたい場合に支障とな
ることがある。 Further, according to such a structure, the integrated circuit element 10 protrudes from the surface of the printed wiring board 20 by at least the thickness thereof, which may be a problem if the mechanism including the printed wiring board 10 is desired to be made thinner. There is.
本考案は、このような点に着目したものであつ
て、その目的は、放熱効果が高くプリント配線板
を含む機構を薄くできる集積回路素子取付機構を
提供することにある。 The present invention has focused on these points, and its purpose is to provide an integrated circuit element mounting mechanism that has a high heat dissipation effect and can make the mechanism including a printed wiring board thin.
（問題点を解決するための手段）
このような目的を達成する本考案は、一方の面
から側面にかけて複数の接続パターンが形成され
他方の面には絶縁部材が設けられた集積回路素子
と、この集積回路素子を嵌め合わせるための開口
部が設けられこの開口部の周囲には集積回路素子
素子の所定の接続パターンと接続される複数の配
線パターンが形成されたプリント配線板と、この
プリント配線板の一方の面に取り付けられた金属
板とからなり、前記集積回路素子はその絶縁部材
面が金属板と接触するようにしてプリント配線板
の開口部に嵌め合わされ、集積回路素子の所定の
接続パターンとプリント配線板の所定の配線パタ
ーンとが接続部材で接続されたことを特徴とす
る。(Means for Solving the Problems) The present invention that achieves the above object includes an integrated circuit element in which a plurality of connection patterns are formed from one side to the other side, and an insulating member is provided on the other side; A printed wiring board is provided with an opening for fitting the integrated circuit element, and a plurality of wiring patterns are formed around the opening to be connected to predetermined connection patterns of the integrated circuit element. and a metal plate attached to one side of the board, and the integrated circuit element is fitted into the opening of the printed wiring board so that the insulating member surface is in contact with the metal plate, and the integrated circuit element is connected to a predetermined connection. It is characterized in that the pattern and a predetermined wiring pattern of the printed wiring board are connected by a connecting member.
（実施例）
以下、図面を用いて本考案の実施例を詳細に説
明する。(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.
第１図は本考案で用いる集積回路素子１０の具
体例を示す構成説明図であり、第４図に示した集
積回路素子１０を絶縁部材１５が設けられた面１
４をプリント配線板１０に対向させるとともに複
数の接続パターン１３が設けられた面１１を露出
させるように裏返した状態を示している。 FIG. 1 is a configuration explanatory diagram showing a specific example of an integrated circuit element 10 used in the present invention, in which the integrated circuit element 10 shown in FIG.
4 is turned over so as to face the printed wiring board 10 and to expose the surface 11 on which a plurality of connection patterns 13 are provided.
第２図は、本考案で用いるプリント配線板２０
の具体例を示す構成説明図である。第２図に示す
ように、プリント配線板２０には集積回路素子１
０を嵌め合わせるための開口部２２が設けられ、
この開口部２２の周囲には集積回路素子１０の所
定の接続パターン１３と接続される複数の配線パ
ターン２３が形成されている。また、プリント配
線板２０の一方の面２４（裏面）には、プリント
配線板２０の補強を兼ねた金属板３０が、プリン
ト配線板２０の両面に配線パターンが設けられて
いる場合には絶縁シート４０を介して、面２４に
配線パターンが設けられていない場合には絶縁シ
ートを介することなく直接に取り付けられてい
る。なお、絶縁シート４０のプリント配線板２０
の開口部２２に対向した部分は切り欠かれてい
る。 Figure 2 shows a printed wiring board 20 used in the present invention.
FIG. 2 is a configuration explanatory diagram showing a specific example. As shown in FIG. 2, a printed wiring board 20 includes an integrated circuit element 1.
An opening 22 for fitting 0 is provided,
A plurality of wiring patterns 23 are formed around this opening 22 to be connected to predetermined connection patterns 13 of the integrated circuit element 10. Further, on one side 24 (back side) of the printed wiring board 20, a metal plate 30 that also serves as reinforcement of the printed wiring board 20 is provided, and if wiring patterns are provided on both sides of the printed wiring board 20, an insulating sheet is provided. If no wiring pattern is provided on the surface 24, it is directly attached via the insulation sheet 40 without using an insulating sheet. Note that the printed wiring board 20 of the insulating sheet 40
The portion facing the opening 22 is cut out.
このような構成において、集積回路素子１０は
その絶縁部材１５の表面が金属板３０と接触する
ようにしてプリント配線板２０の開口部２２に嵌
め合わされ、集積回路素子１０の所定の接続パタ
ーン１３とプリント配線板２０の所定の配線パタ
ーン２３とがはんだなどの接続部材で接続されて
固着される。 In such a configuration, the integrated circuit element 10 is fitted into the opening 22 of the printed wiring board 20 such that the surface of the insulating member 15 is in contact with the metal plate 30, and is connected to the predetermined connection pattern 13 of the integrated circuit element 10. A predetermined wiring pattern 23 of the printed wiring board 20 is connected and fixed with a connecting member such as solder.
第３図は、このようにして集積回路素子１０を
プリント配線板２０に取り付けた状態の一例を示
す断面図である。 FIG. 3 is a cross-sectional view showing an example of a state in which the integrated circuit element 10 is attached to the printed wiring board 20 in this manner.
このように構成することにより、集積回路素子
１０と金属板３０とが絶縁部材１５を介して熱的
に結合されることから、集積回路素子１０が発熱
しても金属板３０を介して効果的に放熱されるこ
とになり、集積回路素子１０の動作が温度上昇に
よつて不安定になることはない。 With this configuration, the integrated circuit element 10 and the metal plate 30 are thermally coupled via the insulating member 15, so even if the integrated circuit element 10 generates heat, it can be effectively prevented via the metal plate 30. As a result, the operation of the integrated circuit element 10 will not become unstable due to a rise in temperature.
また、集積回路素子１０をプリント配線板２０
の開口部２２に嵌め込んでいるので、集積回路素
子１０を取り付けた状態でのプリント配線板２０
を含む厚さを少なくともプリント配線板２０の厚
さ分は薄くでき、機構全体の薄形化を図ることが
できる。 Further, the integrated circuit element 10 is mounted on a printed wiring board 20.
Since the printed wiring board 20 is fitted into the opening 22 of the printed wiring board 20 with the integrated circuit element 10 attached,
The thickness including the printed wiring board 20 can be reduced by at least the thickness of the printed wiring board 20, and the entire mechanism can be made thinner.
なお、上記実施例では、金属板３０がプリント
配線板２０の補強機能を有するものの例について
説明したが、例えばシヤーシの一部を構成するも
のであつてもよい。 In the above embodiment, the metal plate 30 has the function of reinforcing the printed wiring board 20, but the metal plate 30 may constitute a part of the chassis, for example.
（考案の効果）
以上説明したように、本考案によれば、放熱効
果が高くプリント配線板を含む機構を薄くできる
集積回路素子取付機構が実現でき、実用上の効果
は大きい。(Effects of the Invention) As explained above, according to the present invention, an integrated circuit element mounting mechanism can be realized which has a high heat dissipation effect and can reduce the thickness of the mechanism including the printed wiring board, and has great practical effects.
第１図は本考案で用いる集積回路素子の具体例
を示す構成説明図、第２図は本考案で用いるプリ
ント配線板の具体例を示す構成説明図、第３図は
集積回路素子をプリント配線板に取り付けた状態
の一例を示す断面図、第４図は集積回路素子の一
例を示す構成説明図、第５図は従来の取付機構の
一例を示す構成説明図である。
１０……集積回路素子、２０……プリント配線
板、３０……金属板、４０……絶縁シート。
Fig. 1 is a structural explanatory diagram showing a specific example of an integrated circuit element used in the present invention, Fig. 2 is a structural explanatory diagram showing a specific example of a printed wiring board used in the present invention, and Fig. 3 is a printed wiring diagram of an integrated circuit element. FIG. 4 is a cross-sectional view showing an example of a state in which it is attached to a plate, FIG. 4 is a configuration explanatory diagram showing an example of an integrated circuit element, and FIG. 5 is a configuration explanatory diagram showing an example of a conventional mounting mechanism. 10... Integrated circuit element, 20... Printed wiring board, 30... Metal plate, 40... Insulating sheet.
Claims (1)
が形成され他方の面には絶縁部材が設けられた集
積回路素子と、この集積回路素子を嵌め合わせる
ための開口部が設けられこの開口部の周囲には集
積回路素子の所定の接続パターンと接続される複
数の配線パターンが形成されたプリント配線板
と、このプリント配線板の一方の面に取り付けら
れた金属板とからなり、前記集積回路素子はその
絶縁部材面が金属板と接触するようにしてプリン
ト配線板の開口部に嵌め合わされ、集積回路素子
の所定の接続パターンとプリント配線板の所定の
配線パターンとが接続部材で接続されたことを特
徴とする集積回路素子取付機構。 An integrated circuit element with a plurality of connection patterns formed from one side to the other side and an insulating member provided on the other side, and an opening for fitting the integrated circuit element, and the area around this opening is It consists of a printed wiring board on which a plurality of wiring patterns are formed to be connected to a predetermined connection pattern of an integrated circuit element, and a metal plate attached to one side of the printed wiring board, and the integrated circuit element is The connecting member is fitted into the opening of the printed wiring board so that the member surface is in contact with the metal plate, and the predetermined connection pattern of the integrated circuit element and the predetermined wiring pattern of the printed wiring board are connected by the connection member. integrated circuit element mounting mechanism.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985130097U JPH0331092Y2 (en) | 1985-08-27 | 1985-08-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985130097U JPH0331092Y2 (en) | 1985-08-27 | 1985-08-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6245870U JPS6245870U (en) | 1987-03-19 |
| JPH0331092Y2 true JPH0331092Y2 (en) | 1991-07-01 |
Family
ID=31027269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985130097U Expired JPH0331092Y2 (en) | 1985-08-27 | 1985-08-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0331092Y2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2541494B2 (en) * | 1993-12-15 | 1996-10-09 | 日本電気株式会社 | Semiconductor device |
| JP2550477B2 (en) * | 1994-05-27 | 1996-11-06 | 株式会社オーケープリント | Memory device component mounting plate and memory unit |
| BR112021005233B1 (en) | 2018-09-20 | 2024-02-27 | Neuroceuticals Inc. | MEDICAL TUBE POSITION CONFIRMATION SYSTEM |
| CN115427001A (en) | 2020-03-30 | 2022-12-02 | E.Z.N.G科技有限责任公司 | Device and method for nasogastric tube insertion guidance |
-
1985
- 1985-08-27 JP JP1985130097U patent/JPH0331092Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6245870U (en) | 1987-03-19 |
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