JPS645092A - Circuit substrate for high power and hybrid integrated circuit thereof - Google Patents

Circuit substrate for high power and hybrid integrated circuit thereof

Info

Publication number
JPS645092A
JPS645092A JP16181087A JP16181087A JPS645092A JP S645092 A JPS645092 A JP S645092A JP 16181087 A JP16181087 A JP 16181087A JP 16181087 A JP16181087 A JP 16181087A JP S645092 A JPS645092 A JP S645092A
Authority
JP
Japan
Prior art keywords
insulating layer
foil
copper foil
layer
wall thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16181087A
Other languages
Japanese (ja)
Inventor
Kazuo Kato
Tatsuo Nakano
Shinichiro Asai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP16181087A priority Critical patent/JPS645092A/en
Publication of JPS645092A publication Critical patent/JPS645092A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

PURPOSE:To stabilize the adhesive property and the dielectric strength property with respect to an insulating layer and a copper foil, and to prevent the insulating layer from cracking, by superposing an Al foil on the insulating layer of a metallic substrate and by forming a copper foil with wall thickness on the Al foil. CONSTITUTION:A bonding pads 3 of Al foil etched are formed on an insulating layer 5 which is laminated on a metallic substrate 6 of Al or the like. And a copper foil layer 1 with wall thickness of more than 35mum is laminated on each of the bonding posts 3. Moreover, a semiconductor device consisting of a power transistor 7 or the like is mounted on a part of the copper foil layer 1 with wall thickness through an eutectic solder 10. The transistor 7 is connected to other bonding post 3 through an Al wire 9. Therefore, the adhesive strength between the metallic foil layer and the insulating layer increases and being stabilized. Besides, the thermal stress resulting from the difference of expansion coefficient between the metallic substrate and the copper foil is reduced to prevent the insulating layer from being damaged without the dielectric strength being lowered.
JP16181087A 1987-06-29 1987-06-29 Circuit substrate for high power and hybrid integrated circuit thereof Pending JPS645092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16181087A JPS645092A (en) 1987-06-29 1987-06-29 Circuit substrate for high power and hybrid integrated circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16181087A JPS645092A (en) 1987-06-29 1987-06-29 Circuit substrate for high power and hybrid integrated circuit thereof

Publications (1)

Publication Number Publication Date
JPS645092A true JPS645092A (en) 1989-01-10

Family

ID=15742343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16181087A Pending JPS645092A (en) 1987-06-29 1987-06-29 Circuit substrate for high power and hybrid integrated circuit thereof

Country Status (1)

Country Link
JP (1) JPS645092A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61285795A (en) * 1985-06-13 1986-12-16 電気化学工業株式会社 Manufacture of metal based hybrid integrated circuit board
JPS63250164A (en) * 1987-04-07 1988-10-18 Denki Kagaku Kogyo Kk High power hybrid integrated circuit substrate and its integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61285795A (en) * 1985-06-13 1986-12-16 電気化学工業株式会社 Manufacture of metal based hybrid integrated circuit board
JPS63250164A (en) * 1987-04-07 1988-10-18 Denki Kagaku Kogyo Kk High power hybrid integrated circuit substrate and its integrated circuit

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