JPS6431444A - Porcelain substrate for surface mounting - Google Patents

Porcelain substrate for surface mounting

Info

Publication number
JPS6431444A
JPS6431444A JP62188626A JP18862687A JPS6431444A JP S6431444 A JPS6431444 A JP S6431444A JP 62188626 A JP62188626 A JP 62188626A JP 18862687 A JP18862687 A JP 18862687A JP S6431444 A JPS6431444 A JP S6431444A
Authority
JP
Japan
Prior art keywords
layer
porcelain
surface mounting
placing
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62188626A
Other languages
Japanese (ja)
Inventor
Fumiya Numajiri
Kenji Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP62188626A priority Critical patent/JPS6431444A/en
Publication of JPS6431444A publication Critical patent/JPS6431444A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a porcelain substrate for surface mounting with high reliability capable of placing a power IC element by composing the porcelain layer of a part for placing a semiconductor integrated circuit element by partly or all lacking it. CONSTITUTION:A porcelain substrate 1 for surface mounting has a laminated plate formed by laminating copper or copper alloy layers 3 and 4 on both side surfaces of a core material 2 made of Fe-Ni alloy and preferably a clad material 9 in which these three layers are cladded, a region porcelain layer 7 slightly larger than an IC element 13 is lacked in a part for placing the element 13 of the layer 7, and the element 13 is placed directly on the layer 3 or a thin metal layer 5 in the lacked part 11. Accordingly, the matching of the thermal expansion coefficient of the element 12 (Si chip) to the material 9 is enhanced, and the thermal dissipation is largely improved to prevent the Si chip bonded part from releasing and the Si chip from damaging (cracking).
JP62188626A 1987-07-28 1987-07-28 Porcelain substrate for surface mounting Pending JPS6431444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62188626A JPS6431444A (en) 1987-07-28 1987-07-28 Porcelain substrate for surface mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62188626A JPS6431444A (en) 1987-07-28 1987-07-28 Porcelain substrate for surface mounting

Publications (1)

Publication Number Publication Date
JPS6431444A true JPS6431444A (en) 1989-02-01

Family

ID=16226982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62188626A Pending JPS6431444A (en) 1987-07-28 1987-07-28 Porcelain substrate for surface mounting

Country Status (1)

Country Link
JP (1) JPS6431444A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338967A (en) * 1993-01-12 1994-08-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device structure with plated heat sink and supporting substrate
JP2006179791A (en) * 2004-12-24 2006-07-06 Toshiba Corp Semiconductor device
CN102468395A (en) * 2010-11-04 2012-05-23 浙江雄邦节能产品有限公司 Ceramic substrate LED apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338967A (en) * 1993-01-12 1994-08-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device structure with plated heat sink and supporting substrate
US5770468A (en) * 1993-01-12 1998-06-23 Mitsubishi Denki Kabushiki Kaisha Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere
JP2006179791A (en) * 2004-12-24 2006-07-06 Toshiba Corp Semiconductor device
CN102468395A (en) * 2010-11-04 2012-05-23 浙江雄邦节能产品有限公司 Ceramic substrate LED apparatus

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