JPS6422034U - - Google Patents
Info
- Publication number
- JPS6422034U JPS6422034U JP1987116282U JP11628287U JPS6422034U JP S6422034 U JPS6422034 U JP S6422034U JP 1987116282 U JP1987116282 U JP 1987116282U JP 11628287 U JP11628287 U JP 11628287U JP S6422034 U JPS6422034 U JP S6422034U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- circuit network
- power supply
- buried
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案の原理側面図、第２図は本考案
による一実施例の説明図で、ａ１，ａ２は側面図
、ｂは試験を行う場合の説明図、第３図は従来の
説明図で、ａは側面図、ｂは試験を行う場合の説
明図を示す。 図において、１は基板、２は回路網、３は半田
バンプ、４は電源電極、５はグランド電極を示す
。
による一実施例の説明図で、ａ１，ａ２は側面図
、ｂは試験を行う場合の説明図、第３図は従来の
説明図で、ａは側面図、ｂは試験を行う場合の説
明図を示す。 図において、１は基板、２は回路網、３は半田
バンプ、４は電源電極、５はグランド電極を示す
。
Claims (1)
- 【実用新案登録請求の範囲】 回路網２が埋設される基板１、該基板１の一面
に形成される半田バンプ３とを備えたフリツプチ
ツプにおいて、 前記回路網２に電源の供給を行う電源電極４と
グランド電極５とのそれぞれが前記基板１の他面
に露出されることで設けられて成ることを特徴と
するフリツプチツプ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987116282U JPS6422034U (ja) | 1987-07-29 | 1987-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987116282U JPS6422034U (ja) | 1987-07-29 | 1987-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6422034U true JPS6422034U (ja) | 1989-02-03 |
Family
ID=31358676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987116282U Pending JPS6422034U (ja) | 1987-07-29 | 1987-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6422034U (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05335311A (ja) * | 1992-06-02 | 1993-12-17 | Nec Corp | フリップチップ半導体装置及びその製造方法 |
| JP2011014910A (ja) * | 2009-07-06 | 2011-01-20 | Taiwan Semiconductor Manufacturing Co Ltd | 集積回路構造 |
-
1987
- 1987-07-29 JP JP1987116282U patent/JPS6422034U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05335311A (ja) * | 1992-06-02 | 1993-12-17 | Nec Corp | フリップチップ半導体装置及びその製造方法 |
| JP2011014910A (ja) * | 2009-07-06 | 2011-01-20 | Taiwan Semiconductor Manufacturing Co Ltd | 集積回路構造 |