JPS6157536U - - Google Patents

Info

Publication number
JPS6157536U
JPS6157536U JP1984142970U JP14297084U JPS6157536U JP S6157536 U JPS6157536 U JP S6157536U JP 1984142970 U JP1984142970 U JP 1984142970U JP 14297084 U JP14297084 U JP 14297084U JP S6157536 U JPS6157536 U JP S6157536U
Authority
JP
Japan
Prior art keywords
heat dissipation
metal part
electrical connection
integrated circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984142970U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984142970U priority Critical patent/JPS6157536U/ja
Publication of JPS6157536U publication Critical patent/JPS6157536U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

Description

【図面の簡単な説明】
第1図、第2図は従来装置の構造図、第3図第
4図及び第5図は本考案の実施例構造図である。
図において1はフリツプチツプ、2,2′は電気
接続用バンプ、2aは放熱用金属部、3は基板、
3′,3″,33〓はバンプ用導電パターン、
3aは放熱用導電パターン、4は接続子、5は半
田である。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 絶縁基板上にフリツプチツプ型半導体素子
    を実装した混成集積回路装置において、該フリツ
    プチツプ型半導体素子は表面に電気接続用バンプ
    と放熱用金属部を有すると共に該絶縁基板は該電
    気接続用バンプ及び放熱用金属部と夫々対応する
    導電パターン及び放熱用パターンを備え且つ該電
    気接続用バンプと導電パターン間及び放熱用金属
    部と放熱用パターン間を夫々接着するようにした
    ことを特徴とする混成集積回路装置。 (2) 放熱用金属部と放熱用パターン間を接続子
    を介して接着するようにしたことを特徴とする実
    用新案登録請求の範囲第(1)項記載の混成集積回
    路装置。
JP1984142970U 1984-09-21 1984-09-21 Pending JPS6157536U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984142970U JPS6157536U (ja) 1984-09-21 1984-09-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984142970U JPS6157536U (ja) 1984-09-21 1984-09-21

Publications (1)

Publication Number Publication Date
JPS6157536U true JPS6157536U (ja) 1986-04-17

Family

ID=30701283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984142970U Pending JPS6157536U (ja) 1984-09-21 1984-09-21

Country Status (1)

Country Link
JP (1) JPS6157536U (ja)

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