JPS6420609A - Process control for semiconductor - Google Patents

Process control for semiconductor

Info

Publication number
JPS6420609A
JPS6420609A JP17618387A JP17618387A JPS6420609A JP S6420609 A JPS6420609 A JP S6420609A JP 17618387 A JP17618387 A JP 17618387A JP 17618387 A JP17618387 A JP 17618387A JP S6420609 A JPS6420609 A JP S6420609A
Authority
JP
Japan
Prior art keywords
grooves
substrate
impurities
terminals
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17618387A
Other languages
Japanese (ja)
Inventor
Yutaka Iwasaki
Haruhide Fuse
Koji Naito
Yohei Ichikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17618387A priority Critical patent/JPS6420609A/en
Publication of JPS6420609A publication Critical patent/JPS6420609A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To control rapidly the shape of grooves formed on a substrate and the doping process of impurities in the inner surface thereof, by an easy measuring method of resistivity. CONSTITUTION:Grooves 2 are provided on a p-semiconductor substrate 1 and an n<+> layer 3 is formed by being doped with impurities. A region 4 having close-set grooves 2 of n-doping is then formed, and on the surface of the substrate 1 thereabout, connection regions 5-12 are formed. A specified potential is applied to terminals 5 and 9 and the potential differences between terminals 8 and 12 and between terminals 6 and 10 are measured to control the measured values to be within the range of specifications. According to this constitution, the shape of grooves provided in a substrate and the doping process of the impurities in the inner surface thereof can be controlled easily and rapidly.
JP17618387A 1987-07-15 1987-07-15 Process control for semiconductor Pending JPS6420609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17618387A JPS6420609A (en) 1987-07-15 1987-07-15 Process control for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17618387A JPS6420609A (en) 1987-07-15 1987-07-15 Process control for semiconductor

Publications (1)

Publication Number Publication Date
JPS6420609A true JPS6420609A (en) 1989-01-24

Family

ID=16009102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17618387A Pending JPS6420609A (en) 1987-07-15 1987-07-15 Process control for semiconductor

Country Status (1)

Country Link
JP (1) JPS6420609A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012064807A (en) * 2010-09-16 2012-03-29 Elpida Memory Inc Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012064807A (en) * 2010-09-16 2012-03-29 Elpida Memory Inc Method of manufacturing semiconductor device

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