JPS6418252A - Complementary semiconductor device - Google Patents

Complementary semiconductor device

Info

Publication number
JPS6418252A
JPS6418252A JP62175573A JP17557387A JPS6418252A JP S6418252 A JPS6418252 A JP S6418252A JP 62175573 A JP62175573 A JP 62175573A JP 17557387 A JP17557387 A JP 17557387A JP S6418252 A JPS6418252 A JP S6418252A
Authority
JP
Japan
Prior art keywords
low
resistance
regions
fet
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62175573A
Other languages
Japanese (ja)
Inventor
Hideaki Fujitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62175573A priority Critical patent/JPS6418252A/en
Publication of JPS6418252A publication Critical patent/JPS6418252A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance the tolerance in a latch-up by a method wherein a low- resistance layer situated under one FET, a low-resistance region piercing from the low-resistance layer to the surface of a substrate by partitioning both FET's and an insulating region running along side faces of the other FET in the low- resistance region are provided so that the integration density can be enhanced. CONSTITUTION:The following are provided: low-resistance regions 6 piercing from a low-resistance layer 5 to the surface of a substrate 1 by partitioning an n-channel FET(field-effect transistor) 3 and a p-channel FET 4; insulating regions 7 running along side faces of the regions. Contact regions of a well 2 are removed and a region of the well 2 is reduced by that much. Because the well 2 is of a p-type, the low-resistance regions 6 are extracted to a ground potential similar to the contact regions, the low-resistance layer 5 is extracted to the ground potential in a low-resistance state and function in combination also as contacts of the well 2. By this setup, an electric charge of a noise does not remain in the low-resistance layer 5; the tolerance in a latch-up can be enhanced; the integration density of a semiconductor device can be enhanced.
JP62175573A 1987-07-14 1987-07-14 Complementary semiconductor device Pending JPS6418252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62175573A JPS6418252A (en) 1987-07-14 1987-07-14 Complementary semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62175573A JPS6418252A (en) 1987-07-14 1987-07-14 Complementary semiconductor device

Publications (1)

Publication Number Publication Date
JPS6418252A true JPS6418252A (en) 1989-01-23

Family

ID=15998442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62175573A Pending JPS6418252A (en) 1987-07-14 1987-07-14 Complementary semiconductor device

Country Status (1)

Country Link
JP (1) JPS6418252A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7331739B2 (en) 2004-08-12 2008-02-19 Makino Milling Machine Co., Ltd. Method for machining workpiece

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7331739B2 (en) 2004-08-12 2008-02-19 Makino Milling Machine Co., Ltd. Method for machining workpiece

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