JPS6417448A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6417448A
JPS6417448A JP17321787A JP17321787A JPS6417448A JP S6417448 A JPS6417448 A JP S6417448A JP 17321787 A JP17321787 A JP 17321787A JP 17321787 A JP17321787 A JP 17321787A JP S6417448 A JPS6417448 A JP S6417448A
Authority
JP
Japan
Prior art keywords
input signal
signal lines
pull
cross
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17321787A
Other languages
Japanese (ja)
Inventor
Masahiro Fukui
Yoshiyuki Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17321787A priority Critical patent/JPS6417448A/en
Publication of JPS6417448A publication Critical patent/JPS6417448A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To facilitate a pattern design and to make the size of a mask pattern small, by realizing pull up or pull-down by only addition of a pattern of contact on a cell. CONSTITUTION:Input signal lines 1 and 2 are made to cross with a power source line 3 with an insulation layer in between, and input signal lines 1' and 2' are disposed to cross with a ground line 4. When the input signal lines 1, 1' and 2, 2' are made to be on pull-down and pull-up states respectively, a desired mask pattern is realized by forming patterns of contact holes 5 and contact pads 6 additionally on respective regions where the input signal lines 1' cross with the ground line 4 and where the input signal lines 2 cross with the power source line 3. Accordingly a pattern design is facilitated and a size of a mask pattern is made small.
JP17321787A 1987-07-10 1987-07-10 Semiconductor integrated circuit Pending JPS6417448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17321787A JPS6417448A (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17321787A JPS6417448A (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6417448A true JPS6417448A (en) 1989-01-20

Family

ID=15956300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17321787A Pending JPS6417448A (en) 1987-07-10 1987-07-10 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6417448A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50154079A (en) * 1974-05-31 1975-12-11
JPS6297347A (en) * 1985-10-24 1987-05-06 Seiko Epson Corp One chip microcomputer having gate array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50154079A (en) * 1974-05-31 1975-12-11
JPS6297347A (en) * 1985-10-24 1987-05-06 Seiko Epson Corp One chip microcomputer having gate array

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