JPS6415835A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPS6415835A
JPS6415835A JP62172188A JP17218887A JPS6415835A JP S6415835 A JPS6415835 A JP S6415835A JP 62172188 A JP62172188 A JP 62172188A JP 17218887 A JP17218887 A JP 17218887A JP S6415835 A JPS6415835 A JP S6415835A
Authority
JP
Japan
Prior art keywords
rom
test
contents
register
expected value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62172188A
Other languages
Japanese (ja)
Other versions
JPH0646387B2 (en
Inventor
Osamu Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62172188A priority Critical patent/JPH0646387B2/en
Publication of JPS6415835A publication Critical patent/JPS6415835A/en
Publication of JPH0646387B2 publication Critical patent/JPH0646387B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To realize a ROM reading test effective to holding the secret just with addition of a simple test circuit, by supplying the expected value of the ROM contents into a microcomputer from outside to undergo the internal comparison and delivering only the result of the comparison. CONSTITUTION:A ROM 1 is addressed by a program counter 5 of a CPU 2 and an instruction code is fetched by an instruction register 7. Then the instruction code is decoded and the data on the ROM 1, a data memory 16, a port 8, etc., are successively processed by the CPU 2 including an ALU 11. When a ROM test external terminal 3 is activated, a reading test mode of the ROM 1 is set by a test control signal 4 and a control circuit 6. The increment result of the ROM addresses is latched by a register 12 via the counter 5 and at the same time the expected value of the ROM 1 is latched by a register 13. The ALU 11 performs the subtraction of contents of both registers 12 and 13 and the result of this subtraction is delivered outside via a port 14. This operation is repeated and bit '1' is delivered if the ROM contents are not coincident with the expected value of the ROM.
JP62172188A 1987-07-10 1987-07-10 Micro computer Expired - Lifetime JPH0646387B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62172188A JPH0646387B2 (en) 1987-07-10 1987-07-10 Micro computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62172188A JPH0646387B2 (en) 1987-07-10 1987-07-10 Micro computer

Publications (2)

Publication Number Publication Date
JPS6415835A true JPS6415835A (en) 1989-01-19
JPH0646387B2 JPH0646387B2 (en) 1994-06-15

Family

ID=15937208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62172188A Expired - Lifetime JPH0646387B2 (en) 1987-07-10 1987-07-10 Micro computer

Country Status (1)

Country Link
JP (1) JPH0646387B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0701210A2 (en) 1994-09-12 1996-03-13 Nec Corporation Data processor having data bus and instruction fetch bus provided separately from each other
US6393520B2 (en) 1997-04-17 2002-05-21 Matsushita Electric Industrial Co., Ltd. Data processor and data processing system with internal memories

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717063A (en) * 1980-07-04 1982-01-28 Mitsubishi Electric Corp Test circuit of microcomputer
JPS5851369A (en) * 1981-09-24 1983-03-26 Nec Corp Microcomputer with test circuit
JPS6167168A (en) * 1984-09-10 1986-04-07 Nec Corp Microcomputer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717063A (en) * 1980-07-04 1982-01-28 Mitsubishi Electric Corp Test circuit of microcomputer
JPS5851369A (en) * 1981-09-24 1983-03-26 Nec Corp Microcomputer with test circuit
JPS6167168A (en) * 1984-09-10 1986-04-07 Nec Corp Microcomputer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0701210A2 (en) 1994-09-12 1996-03-13 Nec Corporation Data processor having data bus and instruction fetch bus provided separately from each other
EP0701210A3 (en) * 1994-09-12 1996-09-04 Nec Corp Data processor having data bus and instruction fetch bus provided separately from each other
US5706423A (en) * 1994-09-12 1998-01-06 Nec Corporation Data processor having data bus and instruction fetch bus provided separately from each other
US5958074A (en) * 1994-09-12 1999-09-28 Nec Corporation Data processor having data bus and instruction fetch bus provided separately from each other
US6393520B2 (en) 1997-04-17 2002-05-21 Matsushita Electric Industrial Co., Ltd. Data processor and data processing system with internal memories

Also Published As

Publication number Publication date
JPH0646387B2 (en) 1994-06-15

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