JPS6410667A - Manufacture of bipolar transistor - Google Patents

Manufacture of bipolar transistor

Info

Publication number
JPS6410667A
JPS6410667A JP16614987A JP16614987A JPS6410667A JP S6410667 A JPS6410667 A JP S6410667A JP 16614987 A JP16614987 A JP 16614987A JP 16614987 A JP16614987 A JP 16614987A JP S6410667 A JPS6410667 A JP S6410667A
Authority
JP
Japan
Prior art keywords
forming region
out forming
metal
lead
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16614987A
Other languages
Japanese (ja)
Other versions
JP2623575B2 (en
Inventor
Hiroki Hozumi
Hiromi Sasaki
Akio Kashiwanuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62166149A priority Critical patent/JP2623575B2/en
Publication of JPS6410667A publication Critical patent/JPS6410667A/en
Application granted granted Critical
Publication of JP2623575B2 publication Critical patent/JP2623575B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To enable manufacturing a fine product capable of high speed operation, with a simple process, by exposing a base lead-out forming region and a collector lead-out forming region on the surface of a semiconductor substrate, covering an emitter forming region with an insulating layer, and forming, in this state, a conductor layer having metal, on the semiconductor substrate. CONSTITUTION:As a second insulating layer is formed so as to cover an emitter forming region 13a, said region is not contaminated by metal when a conductor layer 25 having metal is formed on a semiconductor substrate 14. After insulating layers 15, 22 are formed on the part except a base lead-out forming region 13a and a collector lead-out forming region 13b, the conductor layer 25 having metal is formed on the semiconductor substrate 14. Therefore, it is possible for the conductor layer 25 not to be formed on the region except the base lead-out forming region 13a and the collector lead-out forming region 13b. On the base lead-out forming region 13a and a collector lead-out forming region 13b, the conducted layer 25 having metal is formed at the same time by self alignment, and a fine product can be manufactured with a simple process.
JP62166149A 1987-07-02 1987-07-02 Manufacturing method of bipolar transistor Expired - Lifetime JP2623575B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62166149A JP2623575B2 (en) 1987-07-02 1987-07-02 Manufacturing method of bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62166149A JP2623575B2 (en) 1987-07-02 1987-07-02 Manufacturing method of bipolar transistor

Publications (2)

Publication Number Publication Date
JPS6410667A true JPS6410667A (en) 1989-01-13
JP2623575B2 JP2623575B2 (en) 1997-06-25

Family

ID=15825966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62166149A Expired - Lifetime JP2623575B2 (en) 1987-07-02 1987-07-02 Manufacturing method of bipolar transistor

Country Status (1)

Country Link
JP (1) JP2623575B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194673A (en) * 1986-02-20 1987-08-27 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194673A (en) * 1986-02-20 1987-08-27 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JP2623575B2 (en) 1997-06-25

Similar Documents

Publication Publication Date Title
JPS5249772A (en) Process for production of semiconductor device
JPS5324277A (en) Semiconductor devic e and its production
JPS5643749A (en) Semiconductor device and its manufacture
JPS6410667A (en) Manufacture of bipolar transistor
JPS5278382A (en) Semiconductor device
JPS5578532A (en) Formation of electrode for semiconductor device
JPS5643740A (en) Semiconductor wafer
KR880014690A (en) CMOS integrated circuit having upper substrate contacts and its manufacturing method
JPS57167659A (en) Manufacture of semiconductor device
JPS56157042A (en) Manufacture of semiconductor device
JPS5246783A (en) Process for production of semiconductor integrated circuit
JPS5263080A (en) Production of semiconductor integrated circuit device
JPS5710963A (en) Semiconductor device and manufacture thereof
JPS647518A (en) Manufacture of semiconductor device
JPS5235584A (en) Manufacturing process of semiconductor device
JPS51113461A (en) A method for manufacturing semiconductor devices
JPS5240061A (en) Semiconductor device and process for production of same
JPS5732664A (en) Semiconductor integrated circuit device
JPS57199251A (en) Semiconductor device
JPS5248974A (en) Process for production of diffusion type semiconductor device
JPS57197863A (en) Semiconductor integrated circuit device
JPS57102068A (en) Semiconductor integrated circuit
JPS5710964A (en) Manufacture of semiconductor device
JPS5232682A (en) Manufacturing process of semiconductor device
JPS5310281A (en) Production of mos type semiconductor integrated circuit

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term
FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 11

Free format text: PAYMENT UNTIL: 20080411