JPS6389264U - - Google Patents
Info
- Publication number
- JPS6389264U JPS6389264U JP18517586U JP18517586U JPS6389264U JP S6389264 U JPS6389264 U JP S6389264U JP 18517586 U JP18517586 U JP 18517586U JP 18517586 U JP18517586 U JP 18517586U JP S6389264 U JPS6389264 U JP S6389264U
- Authority
- JP
- Japan
- Prior art keywords
- pad
- board
- bond pad
- ceramic sub
- soldering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 7
- 238000005476 soldering Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910015365 Au—Si Inorganic materials 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 229910003460 diamond Inorganic materials 0.000 claims 1
- 239000010432 diamond Substances 0.000 claims 1
- 230000005496 eutectics Effects 0.000 claims 1
- 229910002065 alloy metal Inorganic materials 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Description
第1図はこの考案の一実施例を示す斜視図、第
2図は第1図に示したものの断面図、第3図は従
来の混成集積回路装置を示す斜視図、第4図は第
3図に示したものの断面図である。
図において1はセラミツク基板、2,18は回
路パターン、3,13はダイボンドパツド、4,
14はワイヤボンドパツド、5はリードレスチツ
プ部品パツド、6は接続部、7はシリコンチツプ
、8は共晶合金属、9はリードレスチツプ部品、
10は半田、11はボンデイングワイヤ、12は
セラミツクサブ基板、15a,15b,19a,
19bは半田付けパツド、16はスルーホール、
17はベース基板である。なお、各図中同一符号
は同一又は相当部分を示す。
FIG. 1 is a perspective view showing one embodiment of this invention, FIG. 2 is a sectional view of the device shown in FIG. 1, FIG. 3 is a perspective view showing a conventional hybrid integrated circuit device, and FIG. FIG. 3 is a cross-sectional view of what is shown in the figure. In the figure, 1 is a ceramic substrate, 2 and 18 are circuit patterns, 3 and 13 are die bond pads, 4,
14 is a wire bond pad, 5 is a leadless chip component pad, 6 is a connection part, 7 is a silicon chip, 8 is a eutectic alloy metal, 9 is a leadless chip component,
10 is solder, 11 is a bonding wire, 12 is a ceramic sub-board, 15a, 15b, 19a,
19b is a soldering pad, 16 is a through hole,
17 is a base substrate. Note that the same reference numerals in each figure indicate the same or equivalent parts.
Claims (1)
パツドとワイヤボンドパツドとを有し、他方の面
に前記一方の面のダイヤボンドパツド及びワイヤ
ボンドパツドと対応した半田付けパツドを有し、
前記一方の面と他方の面の相対応する各パツドを
接続するスルーホールを有するセラミツクサブ基
板と、このセラミツクサブ基板に取付けられるシ
リコンSiチツプと、前記セラミツクサブ基板の
他方の面の半田付けパツドと対応する半田付けパ
ツドを有するベース基板とで構成され、セラミツ
クサブ基板の前記一方の面において、ダイボンド
パツドにシリコンSiチツプがAu―Si共晶接
合で取付けられ、シリコンSiチツプの電極とワ
イヤボンドパツドとがワイヤボンデイング接続さ
れ、セラミツクサブ基板の前記他方の面の半田付
けパツドと前記ベース基板の半田付けパツドとが
半田付けされた構造となつていることを特徴とす
る混成集積回路装置。 It has a die bond pad and a wire bond pad made of a gold-Au conductor on one side, and a soldering pad on the other side that corresponds to the diamond bond pad and wire bond pad on the one side. death,
A ceramic sub-board having through holes connecting corresponding pads on one side and the other side, a silicon Si chip attached to the ceramic sub-board, and a soldering pad on the other side of the ceramic sub-board. and a base substrate having a corresponding soldering pad, and on the one surface of the ceramic sub-substrate, a silicon Si chip is attached to the die bond pad by Au-Si eutectic bonding, and the electrodes of the silicon Si chip and wires are attached to the die bond pad. A hybrid integrated circuit device characterized in that the soldering pad on the other side of the ceramic sub-board and the soldering pad on the base board are soldered to each other by wire bonding. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18517586U JPS6389264U (en) | 1986-12-01 | 1986-12-01 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18517586U JPS6389264U (en) | 1986-12-01 | 1986-12-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6389264U true JPS6389264U (en) | 1988-06-10 |
Family
ID=31133553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18517586U Pending JPS6389264U (en) | 1986-12-01 | 1986-12-01 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6389264U (en) |
-
1986
- 1986-12-01 JP JP18517586U patent/JPS6389264U/ja active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6389264U (en) | ||
JPS58218130A (en) | Hybrid integrated circuit | |
JPS6237939U (en) | ||
JPS63157934U (en) | ||
JPS63167733U (en) | ||
JPH0189752U (en) | ||
JPH03109342U (en) | ||
JPH01174923U (en) | ||
JPH045640U (en) | ||
JPH0379469U (en) | ||
JPS6194359U (en) | ||
JPS6153854B2 (en) | ||
JPH0420235U (en) | ||
JPS60129159U (en) | semiconductor pressure sensor | |
JPH02104647U (en) | ||
JPS6457656U (en) | ||
JPS60189945A (en) | Chip carrier | |
JPS61131870U (en) | ||
JPH02131353U (en) | ||
JPS61153374U (en) | ||
JPS58195445U (en) | Semiconductor integrated circuit package | |
JPS63147831U (en) | ||
JPH0192143U (en) | ||
JPS63182570U (en) | ||
JPS63140625U (en) |