JPS638490B2 - - Google Patents

Info

Publication number
JPS638490B2
JPS638490B2 JP57142765A JP14276582A JPS638490B2 JP S638490 B2 JPS638490 B2 JP S638490B2 JP 57142765 A JP57142765 A JP 57142765A JP 14276582 A JP14276582 A JP 14276582A JP S638490 B2 JPS638490 B2 JP S638490B2
Authority
JP
Japan
Prior art keywords
alu
data
register
input
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57142765A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5840667A (ja
Inventor
Rene Chebira Pieeru
Peteru Kaezaa Hansu
Geruharuto Ururitsuhi Maibaruto Deiitoritsuhi
Ungeruboetsuku Gotsutofuriido
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5840667A publication Critical patent/JPS5840667A/ja
Publication of JPS638490B2 publication Critical patent/JPS638490B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/786—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using a single memory module

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Microcomputers (AREA)
  • Advance Control (AREA)
JP57142765A 1981-08-19 1982-08-19 マイクロプロセツサ Granted JPS5840667A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP811064302 1981-08-19
EP81106430A EP0072373B1 (en) 1981-08-19 1981-08-19 Improved microprocessor

Publications (2)

Publication Number Publication Date
JPS5840667A JPS5840667A (ja) 1983-03-09
JPS638490B2 true JPS638490B2 (US20110009641A1-20110113-C00116.png) 1988-02-23

Family

ID=8187860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57142765A Granted JPS5840667A (ja) 1981-08-19 1982-08-19 マイクロプロセツサ

Country Status (4)

Country Link
US (1) US4615004A (US20110009641A1-20110113-C00116.png)
EP (1) EP0072373B1 (US20110009641A1-20110113-C00116.png)
JP (1) JPS5840667A (US20110009641A1-20110113-C00116.png)
DE (1) DE3174130D1 (US20110009641A1-20110113-C00116.png)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4577282A (en) 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
JPS6095651A (ja) * 1983-10-31 1985-05-29 Toshiba Corp 記憶装置
JPS6140650A (ja) * 1984-08-02 1986-02-26 Nec Corp マイクロコンピユ−タ
JPS61122747A (ja) * 1984-11-14 1986-06-10 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション デ−タ処理装置
US4747046A (en) * 1985-06-28 1988-05-24 Hewlett-Packard Company Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch
JPS63170736A (ja) * 1987-01-09 1988-07-14 Toshiba Corp マイクロプロセツサ
CA1327080C (en) * 1987-05-26 1994-02-15 Yoshiko Yamaguchi Reduced instruction set computer (risc) type microprocessor
US4926355A (en) * 1987-07-02 1990-05-15 General Datacomm, Inc. Digital signal processor architecture with an ALU and a serial processing section operating in parallel
US4891754A (en) * 1987-07-02 1990-01-02 General Datacomm Inc. Microinstruction sequencer for instructing arithmetic, logical and data move operations in a conditional manner
US4974146A (en) * 1988-05-06 1990-11-27 Science Applications International Corporation Array processor
US5131086A (en) * 1988-08-25 1992-07-14 Edgcore Technology, Inc. Method and system for executing pipelined three operand construct
JP2760808B2 (ja) * 1988-09-01 1998-06-04 株式会社日立製作所 データ処理装置
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
JPH0711332Y2 (ja) * 1989-03-18 1995-03-15 株式会社ゼクセル 熱交換器
KR100272622B1 (ko) * 1991-05-08 2000-11-15 가나이 쓰도무 데이타 처리장치
JPH07248918A (ja) * 1994-03-10 1995-09-26 Matsushita Electric Ind Co Ltd マイクロプロセッサ
US6233599B1 (en) * 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
FR2831288B1 (fr) * 2001-10-18 2004-12-10 St Microelectronics Sa Microprocesseur disposant d'instructions d'echange de valeurs entre deux registres ou deux emplacements memoire
US8185671B2 (en) * 2006-11-03 2012-05-22 Intel Corporation Technique for increasing control and status signal density in a fixed register address space

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578344A (en) * 1978-12-11 1980-06-12 Toshiba Corp Microprogram control system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771141A (en) * 1971-11-08 1973-11-06 Culler Harrison Inc Data processor with parallel operations per instruction
US4086626A (en) * 1974-10-07 1978-04-25 Fairchild Camera And Instrument Corporation Microprocessor system
US4048481A (en) * 1974-12-17 1977-09-13 Honeywell Information Systems Inc. Diagnostic testing apparatus and method
US4106090A (en) * 1977-01-17 1978-08-08 Fairchild Camera And Instrument Corporation Monolithic microcomputer central processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578344A (en) * 1978-12-11 1980-06-12 Toshiba Corp Microprogram control system

Also Published As

Publication number Publication date
EP0072373A3 (en) 1983-06-29
US4615004A (en) 1986-09-30
EP0072373B1 (en) 1986-03-19
JPS5840667A (ja) 1983-03-09
DE3174130D1 (en) 1986-04-24
EP0072373A2 (en) 1983-02-23

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