JPS6373700A - Heat radiation structure of circuit module - Google Patents
Heat radiation structure of circuit moduleInfo
- Publication number
- JPS6373700A JPS6373700A JP61217318A JP21731886A JPS6373700A JP S6373700 A JPS6373700 A JP S6373700A JP 61217318 A JP61217318 A JP 61217318A JP 21731886 A JP21731886 A JP 21731886A JP S6373700 A JPS6373700 A JP S6373700A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- board
- circuit module
- net
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005855 radiation Effects 0.000 title 1
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 230000017525 heat dissipation Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 239000010949 copper Substances 0.000 description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 238000009940 knitting Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概 要〕
回路部品を搭載した基板をヒートシンク上に重ね合わせ
た回路モジュールにおいて、基板の発熱をヒートシンク
を通じて有効に熱放散させかつ基板とヒートシンクとの
間の熱膨張差から生ずる応力を吸収するために、熱伝導
性及び導電性に優れかつ弾性の比較的低い金属リードを
メツシュ状に編んで構成したネットを基板とヒートシン
ク間に挿入しネット上下面の凸部をはんだで点接合する
。[Detailed Description of the Invention] [Summary] In a circuit module in which a board on which circuit components are mounted is stacked on a heat sink, the heat generated by the board is effectively dissipated through the heat sink, and the difference in thermal expansion between the board and the heat sink is reduced. In order to absorb the stress generated by the heat sink, a mesh-like mesh of metal leads with excellent thermal and electrical conductivity and relatively low elasticity is inserted between the board and the heat sink, and the convex parts on the top and bottom of the net are soldered. Do a point joint.
本発明は、回路部品を搭載した基板をヒートシンク上に
重ね合わせた基板の発熱をヒートシンクを通じて熱放散
させるとともに基板とヒートシンクとを電気的に導通さ
せる回路モジュール、特にその放熱構造に関する。The present invention relates to a circuit module in which heat generated by a board on which a circuit component is mounted is superimposed on a heat sink is dissipated through the heat sink, and the board and the heat sink are electrically connected, and particularly to a heat dissipation structure thereof.
従来は、第３図に示すように、高い熱伝導性をうるため
に１同（Ｃｕ ）のヒートシンク１上にアルミナセラミ
ック基板２をはんだ等の接合材３にて面接合させていた
。このアルミナセラミック基板２上には大型集積回路（
ＬＳＩ）４やチップ抵抗５等の回路部品が搭載される。Conventionally, as shown in FIG. 3, in order to obtain high thermal conductivity, an alumina ceramic substrate 2 was surface-bonded onto a Cu heat sink 1 using a bonding material 3 such as solder. A large integrated circuit (
Circuit components such as an LSI (LSI) 4 and a chip resistor 5 are mounted.
上記のような従来の構造によると、ヒートシンクｌを構
成する銅（Ｃｕ）とアルミナセラミック基板２との熱膨
張係数は、銅（Ｃｕ ）が２０Ｘ１０−ｈ、アルミナが
７ＸＩＯ−’と異なるため、両者をはんだで面接合する
と、環境温度の変化に伴う応力歪みにより両者の接合部
にクラックが生じたり、セラミック基板２が割れたりす
る等の問題があった。そこで、本発明では、回路基板と
ヒートシンクとの接合を面接合から点接合に置き換える
ことにより熱膨張係数の差による熱応力歪みを吸収し、
かつ基板の熱を有効にヒートシンクへ放熱し、さらに簡
単な構成で基板とヒートシンク間の電気的接続を達成す
る回路モジュールの放熱構造を提供することである。According to the conventional structure as described above, the thermal expansion coefficients of the copper (Cu) that constitutes the heat sink l and the alumina ceramic substrate 2 are different, 20X10-h for copper (Cu) and 7XIO-' for alumina. When these are joined face-to-face with solder, there are problems such as cracks occurring at the joint between the two and cracking of the ceramic substrate 2 due to stress strain caused by changes in environmental temperature. Therefore, in the present invention, the thermal stress strain caused by the difference in coefficient of thermal expansion is absorbed by replacing the surface bonding with the point bonding between the circuit board and the heat sink.
Another object of the present invention is to provide a heat dissipation structure for a circuit module that effectively dissipates heat from a board to a heat sink and achieves electrical connection between the board and the heat sink with a simple configuration.
本発明によると、回路部品を搭載した基板をヒートシン
ク上に重ね合わせ基板の発熱をヒートシンクを通じて熱
放散させるとともに基板とヒートシンクとを電気的に導
通させる回路モジュールにおいて、熱伝導性及び導電性
に優れかつ弾性の比較的低い金属リードをメツシュ状に
編んで構成した金属製ネットを前記基板とヒートシンク
間に挿入しネット上下面の凸部と前記基板の裏面及びヒ
ートシンクの上面との間をはんだ等の接合材にて点接合
したことを特徴とする回路モジュールの放熱構造が提供
される。According to the present invention, there is provided a circuit module in which a board on which circuit components are mounted is stacked on a heat sink, the heat generated by the board is dissipated through the heat sink, and the board and the heat sink are electrically connected. A metal net formed by knitting metal leads with relatively low elasticity into a mesh shape is inserted between the substrate and the heat sink, and the convex portions on the top and bottom surfaces of the net are joined with the back surface of the substrate and the top surface of the heat sink using solder or the like. A heat dissipation structure for a circuit module is provided, which is characterized in that the heat dissipation structure is point-joined using materials.
金属製ネットの点接合部により回路基板とヒートシンク
との接合が達成され、このネットの構成により回路基板
とヒートシンクの熱膨張係数の差による熱応力歪みが吸
収され、基板の熱はネットを介してヒートシンクへ放熱
され、さらに金属リードより成るネットを介して基板と
ヒートシンク間の電気的接続が達成される。The bonding between the circuit board and the heat sink is achieved by the point joint of the metal net, and the configuration of this net absorbs the thermal stress strain due to the difference in thermal expansion coefficient between the circuit board and the heat sink, and the heat of the board is transferred through the net. Heat is dissipated to the heat sink, and electrical connection between the substrate and the heat sink is achieved via a net made of metal leads.
以下、第１図及び第２図を参照して本発明の実施例につ
いて詳細に説明する。Embodiments of the present invention will be described in detail below with reference to FIGS. 1 and 2.
第１図は本発明の回路モジュールの実施例１の断面図で
ある。アルミナセラミック基板２の上下両面には、あら
かじめ回路パターン（図示せず）が形成されていて、先
ず最初、基板２の表面に大型集積回路（ＬＳＩ）４やチ
ップ抵抗５等の回路部品を通常の錫鉛（ＳｎＰｂ）はん
だ（融点１８３℃）にて搭載する。次に、！Ｍ（Ｃｕ）
のヒートシンク１の上面及び基板２の裏面に公知の方法
で低融点はんだ１５．１６を６０〜１００μの厚さに印
刷形成する。次に、ヒートシンク１上にアルミナセラミ
ック基板２を重ね合わせるに際して、リード製ネット１
０を介在させる。このリード製ネットｌＯは熱伝導性及
び導電性に優れかつ弾性の比較的低い線状の金属リード
１１．１２を縦と横の両方向からメツシュ状に編んで構
成したものである。線状の金属リード１１．１２として
は、例えばリードフレームを構成するような銅（Ｃｕ）
合金や燐青銅又は銅にメッキを施した金属線が適してい
る。FIG. 1 is a sectional view of Embodiment 1 of the circuit module of the present invention. A circuit pattern (not shown) is formed in advance on both the upper and lower surfaces of the alumina ceramic substrate 2, and circuit components such as a large integrated circuit (LSI) 4 and a chip resistor 5 are first placed on the surface of the substrate 2 in a conventional manner. Mounted using tin lead (SnPb) solder (melting point 183°C). next,! M(Cu)
A low melting point solder 15, 16 is printed to a thickness of 60 to 100 μm on the top surface of the heat sink 1 and the back surface of the substrate 2 by a known method. Next, when stacking the alumina ceramic substrate 2 on the heat sink 1, the lead net 1
Interpose 0. This lead net IO is constructed by knitting linear metal leads 11 and 12, which have excellent thermal conductivity and electrical conductivity and relatively low elasticity, into a mesh shape from both the vertical and horizontal directions. As the linear metal leads 11 and 12, for example, copper (Cu), which constitutes a lead frame, is used.
Metal wires plated with alloys, phosphor bronze or copper are suitable.
リード製ネット１０を基板２とヒートシンク１間に重ね
るとネット１０の上下面の凸部が基板２の裏面及びヒー
トシンク１の上面に接触する。ここで、リフローイング
を施すことにより、ヒートシンク１の上面及び基板２の
裏面の低融点はんだ１５．１６が溶融し、ネット１０の
上下面の凸部に点接合する。When the lead net 10 is placed between the substrate 2 and the heat sink 1, the convex portions on the upper and lower surfaces of the net 10 come into contact with the back surface of the substrate 2 and the upper surface of the heat sink 1. By performing reflowing, the low melting point solders 15 and 16 on the top surface of the heat sink 1 and the back surface of the substrate 2 are melted and point-bonded to the convex portions on the top and bottom surfaces of the net 10.
第２図は本発明の回路モジュールの実施例２の断面図で
ある。この実施例２では、リード製ネット２０が、リー
ドフレームとして使用される帯状の金属リード２１．２
２を縦と横の両方向からメツシュ状に編んで構成された
ものである。この場合、はんだによる点接合部はやや広
（なる。その他の構成及び作用は第１実施例の場合と同
様である。FIG. 2 is a sectional view of a second embodiment of the circuit module of the present invention. In this second embodiment, the lead net 20 is a band-shaped metal lead 21.2 used as a lead frame.
2 are knitted in a mesh shape both vertically and horizontally. In this case, the point joints made by solder will be slightly wider.Other configurations and operations are the same as in the first embodiment.
本発明によると、金属製ネットの点接合部を介して回路
基板とヒートシンクとが接合・固定され、回路基板とヒ
ートシンクの熱膨張係数の差による温度変化が生じた場
合の熱応力歪みがネットの構成により充分吸収され、ま
た回路部品より発生した熱は基板自体及び金属製ネット
を介して効果的にヒートシンクへ放熱され、さらに同時
にこのような簡単な構成により金属ネットを介して基板
とヒートシンク間の電気的接続も達成され、耐久性及び
信頬性に冨んだ回路モジュールを実現できる。According to the present invention, a circuit board and a heat sink are bonded and fixed through point joints of a metal net, and thermal stress and distortion of the net when a temperature change occurs due to a difference in coefficient of thermal expansion between the circuit board and the heat sink is reduced. The heat generated by the circuit components is effectively absorbed by the structure, and the heat generated by the circuit components is effectively dissipated to the heat sink through the board itself and the metal net.At the same time, this simple structure also allows the heat generated by the circuit components to be effectively radiated to the heat sink through the metal net. Electrical connections are also achieved, and a circuit module with high durability and reliability can be realized.
第１図は本発明の回路モジュールの実施例１の断面図、
第２図は本発明の回路モジュールの実施例２の断面図、
第３図は従来の回路モジュールの断面図である。
１・・・ヒートシンク、
２・・・基板、
４．５・・・回路部品、
１０・・・金属製ネット、
１１．１２ ・・・リード、
１５、１６・・・はんだ、
２０・・・金属製ネット、
２１．２２ ・・・リード。FIG. 1 is a sectional view of Example 1 of the circuit module of the present invention;
FIG. 2 is a sectional view of Example 2 of the circuit module of the present invention;
FIG. 3 is a sectional view of a conventional circuit module. DESCRIPTION OF SYMBOLS 1... Heat sink, 2... Board, 4.5... Circuit component, 10... Metal net, 11.12... Lead, 15, 16... Solder, 20... Metal Made net, 21.22...Lead.
Claims (1)
シンク（１）上に重ね合わせ基板（２）の発熱をヒート
シンク（１）を通じて熱放散させるとともに基板（２）
とヒートシンク（１）とを電気的に導通させる回路モジ
ュールにおいて、熱伝導性及び導電性に優れかつ弾性の
比較的低い金属リード（１１、１２；２１、２２）をメ
ッシュ状に編んで構成した金属製ネット（１０、２０）
を前記基板（２）とヒートシンク（１）間に挿入しネッ
ト（１０、２０）上下面の凸部と前記基板（２）の裏面
及びヒートシンク（１）の上面との間をはんだ等の接合
材（１５、１６）にて点接合したことを特徴とする回路
モジュールの放熱構造。1. The board (2) on which the circuit components (4, 5) are mounted is stacked on the heat sink (1), and the heat generated by the board (2) is dissipated through the heat sink (1), and the board (2) is placed on top of the heat sink (1).
In a circuit module that electrically connects a heat sink (1) and a metal lead (11, 12; 21, 22) with excellent thermal conductivity and electrical conductivity and relatively low elasticity, the metal lead is woven into a mesh shape. Made net (10, 20)
is inserted between the substrate (2) and the heat sink (1), and a bonding material such as solder is inserted between the convex portions on the top and bottom surfaces of the net (10, 20) and the back surface of the substrate (2) and the top surface of the heat sink (1). (15, 16) A heat dissipation structure for a circuit module characterized by point-joining.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61217318A JPS6373700A (en) | 1986-09-17 | 1986-09-17 | Heat radiation structure of circuit module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61217318A JPS6373700A (en) | 1986-09-17 | 1986-09-17 | Heat radiation structure of circuit module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6373700A true JPS6373700A (en) | 1988-04-04 |
Family
ID=16702287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61217318A Pending JPS6373700A (en) | 1986-09-17 | 1986-09-17 | Heat radiation structure of circuit module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6373700A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8933568B2 (en) | 2010-03-12 | 2015-01-13 | Mitsubishi Electric Corporation | Semiconductor device |
-
1986
- 1986-09-17 JP JP61217318A patent/JPS6373700A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8933568B2 (en) | 2010-03-12 | 2015-01-13 | Mitsubishi Electric Corporation | Semiconductor device |
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