JPH01501990A - How to connect items such as chip packages without lead wires - Google Patents

How to connect items such as chip packages without lead wires

Info

Publication number
JPH01501990A
JPH01501990A JP63501263A JP50126388A JPH01501990A JP H01501990 A JPH01501990 A JP H01501990A JP 63501263 A JP63501263 A JP 63501263A JP 50126388 A JP50126388 A JP 50126388A JP H01501990 A JPH01501990 A JP H01501990A
Authority
JP
Japan
Prior art keywords
printed circuit
pads
circuit board
chip package
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63501263A
Other languages
Japanese (ja)
Other versions
JPH0719952B2 (en
Inventor
ペサベント，フイリップ・ブイ
Original Assignee
ヒューズ・エアクラフト・カンパニー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ヒューズ・エアクラフト・カンパニー filed Critical ヒューズ・エアクラフト・カンパニー
Publication of JPH01501990A publication Critical patent/JPH01501990A/en
Publication of JPH0719952B2 publication Critical patent/JPH0719952B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 リード線のないチップパッケージ等の物品を接続する方法発明の背景 この発明は、リード線のないチップ支持体上のパッドから関係する印刷回路板上 の関係するパッドに金属導体を接続するために超音波溶接を使用してリード線の ないチップパッケージを接続かる方法に関するものである。[Detailed description of the invention] Background of the invention: Method for connecting articles such as chip packages without lead wires This invention provides a method for connecting pads on chip supports without leads to associated printed circuit boards. of the lead wires using ultrasonic welding to connect the metal conductors to the relevant pads of the The present invention relates to a method for connecting chip packages that are not compatible.

リード線のないチップ支持体のパッケージはその下面にパッドを設けられている 。これらのパッドは集積回路チップを収容して保護しているパッケージ中で集積 回路チップに接続されている。この接続は対応するはんだパッドを表面に有する 印刷回路板上にこのパッケージを置くことによって行われる。リード線のないチ ップパッケージは位置を固定され、気相ろう付けによりパッドのはんだの再溶融 によって１工程で電気的に接続される。このような接続方法は多くの場合に有用 であるが、チップが電気的にさらに複雑になり、その結果リード線の数が非常に 多くなり、チップパッケージの下面周縁を取巻くパッド密度が高くなるときには 接続が非常に困難になる。チップパッケージが高密度であり、約６０パツド以上 の接続が行われるとき、パッドに接続される印刷回路板上の配線は互いに接近し 、そのため接近した間隔のためにはんだが配線間を短絡し、またパッド間でもさ らにそのような短絡がしばしば生じる。The chip support package without leads has pads on its underside. . These pads are integrated in the package that houses and protects the integrated circuit chip. connected to a circuit chip. This connection has a corresponding solder pad on the surface This is done by placing this package on a printed circuit board. Chi without lead wire The pad package is fixed in position and the solder on the pads is remelted by vapor phase brazing. electrical connection is made in one step. This type of connection is useful in many cases However, the chip becomes more electrically complex, resulting in a much larger number of leads. When the pad density surrounding the bottom edge of the chip package increases, Connection becomes very difficult. The chip package is high density, approximately 60 pads or more When connections are made, the traces on the printed circuit board that are connected to the pads are close together. , so the close spacing causes solder to short between traces and also between pads. Moreover, such short circuits often occur.

パッド間の間隔をもつと大きくするようにリード線のないチップパッケージを大 きく作ることは別の問題を強調することになる。複雑な電子回路においては、印 刷回路板上のスペースは非常に貴重なものであり、必要以上に大きいパッケージ は必要な広いスペースを無駄にすることになる。さらに複雑な電子回路および必 要な多数の接続数によって、或いははんだによる短絡の危険を減少させるために パッド間の間隔をもつと大きくすることによって生じる大きなパッケージでは熱 膨張の問題が重大なものとなる。リード線のないチップパッケージは印刷回路板 とは別個の材料であり、そのため温度変化によって寸法差がリード線のないチッ プパッケージのはんだパッドに歪みを生成する。これらの歪みが過大になると、 はんだパッドにクラックが生じる。これははんだパッドをより高いレベルに設け ることにより、温度変化によって生じた歪みが弾性または延性偏向によってパッ ド中で吸収されるようにする必要を生じる。Chip packages without leads can be enlarged to increase the spacing between pads. Making it too loud will only emphasize another issue. In complex electronic circuits, Space on printed circuit boards is at a premium, and packages that are larger than necessary would waste much needed space. More complex electronic circuits and To reduce the risk of short circuits due to the large number of connections required or due to soldering Larger packages generate heat due to increased spacing between pads. The problem of expansion becomes significant. A chip package without leads is a printed circuit board It is a separate material from creates distortion in the solder pads of the package. When these distortions become excessive, Cracks appear on the solder pads. This places the solder pads at a higher level. This allows the strain caused by temperature changes to be compressed by elastic or ductile deflection. This creates a need for absorption in the water.

したがって、通常のはんだ再溶融によるリード線のないチップパッケージの取付 けは、接続されるパッドの数が増加し、パッドおよび印刷回路板上の配線が高密 度のときには問題を生じる。したがって、高密度パッケージ、特に高密度のリー ド線のないチップパッケージの対応する印刷回路板への接続のための方法が必要 である。Therefore, the installation of chip packages without leads by normal solder remelting This increases the number of connected pads and increases the density of pads and traces on printed circuit boards. Problems arise when the degree is high. Therefore, high-density packages, especially high-density lead Need a method for connecting a chip package to a corresponding printed circuit board without lead wires It is.

発明の概要 この発明を理解するために、本質的に概説すれば、この発明は、リード線のない チップパッケージを支持印刷回路板へ接続する方法、およびその接続方法に特に 適したリード線のないチップパッケージならびに完全なアセンブリに関するもの であり、その方法では、リード線のないチップパッケージを関連する印刷回路板 に機械的に取付け、導体をパッケージ上のバットおよび印刷回路板上の対応する バットに取付ける。Summary of the invention In order to understand this invention, an essential overview of the invention is to provide a non-lead wire In particular, how to connect a chip package to a supporting printed circuit board and how to do so. Concerning suitable leadless chip packages as well as complete assemblies In that way, the chip package without leads can be connected to the associated printed circuit board. mechanically attach the conductors to the butts on the package and the corresponding parts on the printed circuit board. Attach to the bat.

したがって、この発明の目的および効果は、熱膨張による歪みおよび応力により はんだ接続部にクラックが発生する危険がなく信頼性のある接続ができるような 高密度のリード線のないチップパッケージに特に有用な、リード線のないチップ パッケージを対応する印刷回路板に取付ける方法を提供することである。Therefore, the purpose and effect of the present invention is that the strain and stress caused by thermal expansion This allows reliable connections to be made without the risk of cracks forming in the solder joints. Leadless chips, especially useful for high-density leadless chip packages It is an object of the present invention to provide a method for attaching a package to a corresponding printed circuit board.

この発明の別の目的および効果は、接続が危険な温度増加を生じないで行われる ようにチップパッケージ上のパッドおよび印刷回路板上の対応するパッドに超音 波溶接される金属導体を使用することによってリード線のないチップパッケージ を対応する印刷回路板に接続する方法を提供することである。Another object and advantage of the invention is that the connection is made without dangerous temperature increases. Ultrasound to the pads on the chip package and the corresponding pads on the printed circuit board so that Chip package without leads by using metal conductors that are wave welded and a corresponding printed circuit board.

この発明のさらに別の目的および効果は、印刷回路板が焼けることをなくシ、は んだメッキをなくシ、接続システムの大きな制御作用によって高い生産効率の結 果生成されるはんだによる短絡をなくし、熱膨張の問題を解消し、充分に自動化 された方法を提供するように約６０以上の多数のリードを有するリード線のない チップパッケージを印刷回路板に接続する方法を提供することである。Still another object and effect of the invention is to prevent printed circuit boards from burning. The elimination of solder plating results in high production efficiency due to the large control action of the connection system. Eliminates short circuits caused by solder generated by the process, eliminates thermal expansion issues, and is fully automated. leadless method with a large number of leads of about 60 or more An object of the present invention is to provide a method for connecting a chip package to a printed circuit board.

この発明のその他の目的および効果は以下の明細書、請求の範囲および添附図面 の検討によって明白になるであろう。Other objects and effects of this invention can be found in the following specification, claims, and accompanying drawings. This will become clear after considering the above.

添附図面において、 第１図は、この発明の第１の好ましい方法による接続を示しており、リード線の ないチップパッケージのコーナーと印刷回路板のコーナーを示している。In the attached drawings, FIG. 1 shows the connection according to the first preferred method of the invention, in which the leads are No chip package corners and printed circuit board corners are shown.

第２図は、この発明の第２の好ましい方法による接続を示す同様の図である。FIG. 2 is a similar diagram showing a second preferred method of connection of the invention.

第３図は、この発明の第３の好ましい方法による接続を示す同様の図である。FIG. 3 is a similar diagram showing a third preferred method of connection of the invention.

好ましい実施例の説明 第１図は印刷回路板１２の上面上に上面を下にして取付けられたリード線のない チップ支持体パッケージ１０を示している。Description of the preferred embodiment FIG. 1 shows a printed circuit board 12 with no leads installed top side down on the top surface of a printed circuit board 12. A chip support package 10 is shown.

印刷回路板１２はあかじめ定められたパターンにしたがってその表面に形成され た回路配線を有し、誘電体材料で構成されている。印刷回路板１２の上面１４に は回路配線があり、底面にも回路配線があってもよく、また１以上の中間配線層 があってもよい。１以上の配線層があるとき複数の配線は適当に接続される。こ の例では回路配線（図示せず）は印刷回路板１２の上面１４上のパッドで終端し ている。パッド１６および１８はパッドの一つの列の端部にあり、一方バッド２ ０および２２は別のパッドの列の端部にあり、パッケージ１０の隣接する縁部２ ４゜２６と整列している。印刷回路板１２上のパッドは金、銅、銀、アルミニウ ム、またはニッケルで作ることができる。最も普通の材料は銅であり、最も好ま しいのは金である。この発明の方法は特に高密度パッケージに有用であり、その 結果高い接続密度を有しているという事実から、パッドはパッケージ１０の四方 の縁部の全てに存在するものと考えられ、コーナーを廻って延在し、パッケージ １０の底面２８上にある。The printed circuit board 12 is formed on its surface according to a predetermined pattern. It has circuit wiring and is made of dielectric material. on the top surface 14 of the printed circuit board 12 has circuit wiring, may also have circuit wiring on the bottom surface, and has one or more intermediate wiring layers. There may be. When there is one or more wiring layers, the plurality of wirings are connected appropriately. child In this example, circuit traces (not shown) terminate at pads on top surface 14 of printed circuit board 12. ing. Pads 16 and 18 are at the ends of one row of pads, while pads 2 0 and 22 are at the end of another row of pads, adjacent edge 2 of package 10. It is aligned at 4°26. Pads on printed circuit board 12 may be made of gold, copper, silver, or aluminum. It can be made from aluminum or nickel. The most common material is copper, and the most preferred What matters is money. The method of this invention is particularly useful for high-density packaging; Due to the fact that it has a high connection density as a result, the pads are placed on all sides of the package 10. It is considered to be present on all edges of the package, extending around the corners and 10 on the bottom surface 28.

パッド３０．３２．３４および３６が特にパッケージ１０上に示されている。同 様のパッドがパッケージ１０の４辺に沿って延在し、コーナーを廻って隣接する 底面２８に延在している。パッケージ１０上のパッドは金、銅、銀、アルミニウ ム、またはニッケルで作られている。最も普通で、最も好ましい材料は金である 。Pads 30, 32, 34 and 36 are specifically shown on package 10. same pads extending along the four sides of the package 10 and adjacent around the corners. It extends to the bottom surface 28. The pads on package 10 are made of gold, copper, silver, or aluminum. made of aluminum or nickel. The most common and most preferred material is gold .

チップ支持体パッケージ１０は特に底面２８が印刷回路板の頂面に面するように 設計されているから、図において２８で示した面は底面として説明されている。The chip support package 10 is particularly configured such that the bottom surface 28 faces the top surface of the printed circuit board. By design, the surface designated 28 in the figures is described as the bottom surface.

リード線のないチップ支持体パッケージ１０の通常の使用ではチップ支持体パッ ケージ１０の底面２８にあるパッドの部分の位置に正確に対応して印刷回路板の 上面に配置されたパッドがある。したがって通常のパッケージ１０の使用におい ては各パッドは再溶融はんだによって印刷回路板の上面に配置された対応するパ ッドに接続される。しかしながら、この発明の実施例の場合にはパッケージ１０ はその底面２８を上にして接着剤３８により印刷回路板の上面の適当な位置に固 定されている。電気的接続は各パッドに接続された導体によって行われる。導体 は方形、三角形、円形、楕円形等の断面形状のものでよい。最も好ましい形状は 円形断面の丸い線である。接続は超音波溶接、熱圧縮接続、ボール接続、ウェッ ジ接続または熱音響的接続等により行うことができる。これらの接続方法はいず れも１５０℃以下で行うことができる。したがって導体４０はパッド１８．３０ と接続され、導体４２はパッド１８．３２とその端部で接続され、導体４４はパ ッド２０．３４とその端部で接続され、導体４６はパッド２２．３６とその端部 で接続される。第１図に示されたその他の導体はそれぞれ対応するパッドにその 端部が接続されている。前述のように導体は方形、三角形、円形、楕円形等の断 面形状のものでよい。最も好ましい形状は円形断面の丸線である。導体として使 用する適当な材料には金、銅、ニッケル、アルミニウム等があり、金が好ましい 。パッケージｌＯはセラミックパッケージであり、そのパッド３０乃至８Ｂ等は 通常金のパッドである。印刷回路板１２は水晶を混入したポリイミドであること が好ましく、パッドＩＢ乃至２２等は通常銅である。前述のようにこのブロセッ スでは大きい、高密度のリード線のないパッケージを接続する。リード線のない パッケージとしては６０本以上のリードを有するものが適当である。最も好まし い構造は金の丸線よりなる導体が熱音響的ボール接続またはウェッジ接続により 両側で接続されるものである。好ましい完全な組立て法の形態では、まず熱音響 的ボール接続またはウェッジ接続により印刷回路板上のパッドに接続し、それか ら同じ接続方法でパッケージ上の適当なパッドに導体を取付け、続いて第２の取 付は部を越えて延在する線を切断する。In normal use of the chip carrier package 10 without leads, the chip carrier package on the printed circuit board in exact correspondence with the location of the pads on the bottom surface 28 of the cage 10. There is a pad placed on the top surface. Therefore, when using normal package 10, Each pad is connected to a corresponding pad placed on top of the printed circuit board by remelting solder. connected to the head. However, in embodiments of the invention, package 10 is fixed in place on the top surface of the printed circuit board with adhesive 38 with its bottom side 28 facing up. has been established. Electrical connections are made by conductors connected to each pad. conductor may have a cross-sectional shape such as rectangular, triangular, circular, or oval. The most preferred shape is It is a round line with a circular cross section. Connections are ultrasonic welding, thermocompression connections, ball connections, and welding. This can be done by dielectric connection, thermoacoustic connection, or the like. There are no connection methods for these. Both can be carried out at 150°C or lower. Therefore conductor 40 is connected to pad 18.30 , conductor 42 is connected at its end to pad 18.32, and conductor 44 is connected to pad 18.32 at its end. conductor 46 is connected to pad 20.34 at its end, and conductor 46 is connected to pad 22.36 at its end. Connected with The other conductors shown in Figure 1 are attached to their respective pads. The ends are connected. As mentioned above, conductors can have square, triangular, circular, oval, etc. It may be a surface shape. The most preferred shape is a round wire with a circular cross section. used as a conductor Suitable materials for use include gold, copper, nickel, aluminum, etc., with gold being preferred. . Package IO is a ceramic package, and its pads 30 to 8B etc. Usually a gold pad. The printed circuit board 12 is made of polyimide mixed with crystal. is preferred, and pads IB to 22, etc. are usually copper. As mentioned above, this broset Connect large, high-density leadless packages. without lead wire A suitable package is one having 60 or more leads. most preferred The structure consists of conductors made of round gold wires connected by thermoacoustic ball or wedge connections. It is connected on both sides. In the preferred form of complete assembly method, the thermoacoustic Connect to pads on a printed circuit board with a standard ball or wedge connection; Attach the conductors to the appropriate pads on the package using the same connection method from the Attachment cuts lines that extend beyond the section.

プロセスの工程は印刷回路板上にリード線のないパッケージを位置させ、接着剤 で固定する工程を含む。その後組合わせられた構造は清浄にされ、導体の端部が 対応するパッドに上述のようにあまり温度を高めることなく　（１５０℃以上に しない）接続される。これは応力を無くして信頼性のある接続を与える。The process steps involve positioning the package without leads on the printed circuit board and applying adhesive Including the process of fixing with. The assembled structure is then cleaned and the ends of the conductors are As mentioned above, without raising the temperature too much (over 150℃) on the corresponding pad. (not) connected. This eliminates stress and provides a reliable connection.

第１図で、パッケージ１０は標準のリード線のないチップ支持体パッケージであ り、裏返した形で配置されている。第２図に示されたものではパッケージ１０の 代わりにリード線のないチップ支持体パッケージ５０が同様の印刷回路板１２上 に取付けられている。パッケージ５０もまたリード線のないチップ支持体パッケ ージであり、セラミックで作られ、適当な印刷回路板１２の上面の対応するパッ ドと結合するためにその外側にパッドを備えている。この場合にはパッケージ５ ０の上面５２は印刷回路板１２とは反対側であり、底面５４が接着剤５Ｂによっ て印刷回路板１２の上面１４に固定されている。パッケージ５０上のパッドが接 続のためにアクセスできるようにするために、通常は底面に短い長さで延在し側 縁部５８および６０では途中までしか立上がっていないパッケージ５０上のパッ ドは、上方まで延在して上面にもパッドが存在するように上面５２でも短い長さ で延在するように延長されている。したがって、パッケージ５０はその底面（図 で下面）のパッドが通常のようにはんだの再溶融により印刷回路板１２の対応す るパッドにはんだ付けされている。しかしながら、パッドはまた上面にも延在し 、図ではパッド６２．６４．８６．６８として示されている。したがって、パッ ケージ５０は、側縁部に隣接する底面を横切り、側縁部に沿って走り、側縁部に 隣接する上面を横切って延在する同じパッドを有する特別の構造である。このよ うにして、パッケージ５０は標準のはんだ再溶融の形式の取付けを使用し、また この発明による方法によって接続される。この方法は、接続用リード線を上述の ような接続方法によって対応するパッドに上述のように接続するものである。導 体７２．７４．７６が第２図に特に示されている。パッケージおよび印刷回路板 の両者にはそれ以外にもパッドがあり、別の導体で適当なパッドと接続されてい る。導体７０はパッド１６と６２を接続し、導体７２はパッド１８と６４を接続 し、導体７４はパッド２０と６６を接続し、導体７６はパッド２２と６８を接続 している。バッド６２乃至６８の材料および導体７０乃至７６の材料および形状 は前述したものと同じである。In FIG. 1, package 10 is a standard leadless chip carrier package. It is arranged upside down and upside down. In the one shown in FIG. Instead, a leadless chip carrier package 50 is mounted on a similar printed circuit board 12. installed on. Package 50 is also a chip support package without leads. is made of ceramic and has a corresponding pad on the top surface of a suitable printed circuit board 12. It has a pad on the outside for joining with the pad. In this case package 5 The top surface 52 of 0 is opposite to the printed circuit board 12, and the bottom surface 54 is coated with adhesive 5B. and is fixed to the top surface 14 of the printed circuit board 12. The pads on the package 50 are connected. Usually extends a short length to the bottom and side to provide access for connection. At edges 58 and 60, the pads on package 50 are only partially raised. The pad has a short length on the top surface 52 so that it extends upward and there is a pad on the top surface as well. It has been extended to extend. Therefore, the package 50 has its bottom surface (Fig. The pads on the bottom surface of the printed circuit board 12 are normally removed by remelting the solder. It is soldered to the pad. However, the pad also extends to the top surface. , shown as pads 62.64.86.68 in the figure. Therefore, the patch The cage 50 runs across the bottom surface adjacent the side edge, runs along the side edge, and runs along the side edge. A special structure with identical pads extending across adjacent top surfaces. This way In this way, the package 50 uses standard solder remelt type installation and connected by the method according to the invention. This method connects the connection lead wires as described above. The connection method is used to connect the corresponding pad as described above. Guidance The bodies 72, 74, 76 are particularly shown in FIG. packaging and printed circuit boards Both have other pads and are connected to the appropriate pad by another conductor. Ru. Conductor 70 connects pads 16 and 62, and conductor 72 connects pads 18 and 64. conductor 74 connects pads 20 and 66, and conductor 76 connects pads 22 and 68. are doing. Materials of the pads 62 to 68 and materials and shapes of the conductors 70 to 76 is the same as described above.

第３図は、リード線のないチップ支持体パッケージ８０の印刷回路板１２への取 付けを示している。この場合には、適当な回路配線と適当な位置の接続バッドを 備えた同じ印刷回路板が使用されている。パッケージ８０はこの発明の方法を利 用するために特別の形状にされている。リード線のないチップ支持体パッケージ は通常回路配線およびパッドを適当に備え、適当な物理的形態を有するセラミッ ク材料の複数の層から構成されている。これらの層は積層され、加熱されて一体 構造とされる。パッケージ８０の場合に上の層８２はパッドが設けられる棚部８ Ｂを形成するために下の層８４よりも小さくされている。これらのパッドはパッ ケージ中でチップに内部で接続されている。パッド８ｇ、　９０．９２．９４は 接続のためにアクセスできるように外縁部に隣接してこの棚部８６上に設けられ ている。FIG. 3 shows the mounting of a leadless chip carrier package 80 onto a printed circuit board 12. It shows the attachment. In this case, connect appropriate circuit wiring and connection pads at appropriate locations. The same printed circuit board is used. Package 80 utilizes the method of this invention. It is specially shaped for use. Chip support package without leads is usually a ceramic material with suitable circuit traces and pads and a suitable physical form. consists of multiple layers of solid material. These layers are laminated and heated to unite It is considered to be a structure. In the case of the package 80, the upper layer 82 is the shelf 8 on which the pad is provided. B is made smaller than the underlying layer 84. These pads Internally connected to the chip in a cage. Pad 8g, 90.92.94 is Provided on this shelf 86 adjacent the outer edge for access for connection. ing.

符号を付された以外の多数のパッドが図示されており、それらはパッケージ８０ の四周に沿って配置されていることが好ましい。この発明による方法は６０以上 のリードを有するパッケージで特に有用であるが、その中の一部のものしか図示 されておらず、また符号が付けられていない。パッケージ８０の印刷回路板１２ への取付けは前述のように接着剤によって行われ、パッケージ上のパッドと印刷 回路板上のパッドとの接続も前述のような方法で行われる。導体９６．９８．１ ００　、１０２には符号が付されている。これらの導体はそれぞれパッド１Ｂと ８８、パッド１８と９０、パッド２０と９２、パッド２２と９４を接続している 。A number of pads other than those labeled are shown and are included in the package 80. It is preferable that they are arranged along the four peripheries. There are over 60 methods according to this invention. is particularly useful for packages with leads, only some of which are shown. not marked and not labeled. Printed circuit board 12 in package 80 Attachment to the pads and printing on the package is done by adhesive as described above. Connections to pads on the circuit board are also made in the manner described above. Conductor 96.98.1 00 and 102 are labeled. These conductors are connected to pads 1B and 1B, respectively. 88, connecting pads 18 and 90, pads 20 and 92, and pads 22 and 94 .

導体は前述のようなものであり、パッケージ、印刷回路板および種々のパッドの 材料も前述の通りである。この発明による接続方法は印刷回路板が焼けることを なくシ、はんだのメッキの必要をなくシ、はんだによる短絡を生じることがなく 、パラメータの制御が増大し、熱膨張の問題がなくなることにより高い生産性を 与える。Conductors are as described above and are used in packages, printed circuit boards and various pads. The materials are also as described above. The connection method according to this invention prevents the printed circuit board from burning. Eliminates the need for solder plating and eliminates short circuits caused by solder. , higher productivity due to increased parameter control and elimination of thermal expansion issues. give.

この発明は現在としての最良のものについて説明されたが、種々の変形や、モー ドや、実施態様が同等発明力を必要とすることなく当業者の能力の範囲で可能で あることは明白である。Although this invention has been described in its current best form, there are many modifications and variations to this invention. The methods and embodiments are possible within the ability of a person skilled in the art without requiring equivalent inventiveness. One thing is clear.

したがって、この発明の技術的範囲は請求の範囲の記載によって決定されるべき ものである。Therefore, the technical scope of this invention should be determined by the claims. It is something.

国際調査報告 国際調査報告 υＳεε００１４６ ＳＡ　２０４９２international search report international search report υSεε00146 SA　20492

Claims (26)

【特許請求の範囲】[Claims] １．印刷回路板上面のパッドに隣接して印刷回路板上のパッドと同じ方向にリー ド線のないチップパッケージ上のパッドが向くようにリード線のないチップパッ ケージの方向を定めてリード線のないチップパッケージを印刷回路板上に配置し 、チップパッケージ上の上方を向いたパッドと印刷回路板上の上方を向いた隣接 するパッドとの間に電気導体を接続する過程を含むリード線のないチップパッケ ージの接続方法。1. Leads adjacent to the pads on the top side of the printed circuit board and in the same direction as the pads on the printed circuit board. Place the chip pad without leads so that the pads on the chip package without leads are facing. Orient the cage and place the leadless chip package on the printed circuit board. , an upwardly facing pad on the chip package and an upwardly facing adjacent pad on the printed circuit board. chip package without lead wires, which includes the process of connecting electrical conductors between the pads How to connect the page. ２．電気導体を接続する過程に先立って金、銅、ニッケル、およびアルミニウム からなる群から導体を選択する過程を含む請求の範囲１記載の方法。2. gold, copper, nickel, and aluminum prior to the process of connecting electrical conductors 2. The method of claim 1, including the step of selecting a conductor from the group consisting of: ３．円形、方形、三角形および楕円形の断面を有する導体からなる群から導体を 選択する過程を含む請求の範囲１記載の方法。3. A conductor from the group consisting of conductors with circular, square, triangular and elliptical cross sections. 2. The method of claim 1, including the step of selecting. ４．円形、方形、三角形および楕円形の断面を有する導体からなる群から導体を 選択する過程を含む請求の範囲２記載の方法。4. A conductor from the group consisting of conductors with circular, square, triangular and elliptical cross sections. 3. The method of claim 2, including the step of selecting. ５．電気導体を接続する過程は、超音波溶接、熱圧縮接続、ボール接続、ウエッ ジ接続および熱音響的接続からなる接続過程の群から選択される請求の範囲１記 載の方法。5. The process of connecting electrical conductors includes ultrasonic welding, thermocompression connections, ball connections, and welding. Claim 1 selected from the group of connection processes consisting of thermoacoustic connection and thermoacoustic connection. How to put it on. ６．電気導体を接続する過程は、超音波溶接、熱圧縮接続、ボール接続、ウエッ ジ接続および熱音響的接続からなる接続過程の群から選択される請求の範囲４記 載の方法。6. The process of connecting electrical conductors includes ultrasonic welding, thermocompression connections, ball connections, and welding. Claim 4, wherein the connection process is selected from the group consisting of thermoacoustic connection and thermoacoustic connection. How to put it on. ７．チップパッケージを接着剤によって印刷回路板の上面に固定する過程を含む 請求の範囲１記載の方法。7. Involves the process of fixing the chip package to the top surface of the printed circuit board by adhesive The method according to claim 1. ８．導体をそれらの間に接続することによってパッドを電気的に接続する過程に 先立って印刷回路板およびリード線のないチップパッケージの清浄化過程が行わ れる請求の範囲１記載の方法。8. In the process of electrically connecting pads by connecting conductors between them A cleaning process for printed circuit boards and chip packages without leads is carried out first. The method according to claim 1. ９．チップパッケージを接着剤によって印刷回路板の上面に固定する過程を含む 請求の範囲６記載の方法。9. Involves the process of fixing the chip package to the top surface of the printed circuit board by adhesive The method according to claim 6. １０．リード線のないチップパッケージの底面から上面にパッドを延長させ、こ の延長はチップパッケージの印刷回路板上への配置の前に行われ、それにより印 刷回路板の上面への方向を向いた部分と印刷回路板上のパッドと同じ方向を向い た部分とをチップパッケージ上のパッドが有する請求の範囲１記載の方法。10. This is done by extending the pad from the bottom to the top of the chip package without leads. The extension is done prior to placement of the chip package onto the printed circuit board, thereby The part facing towards the top of the printed circuit board and the same direction as the pads on the printed circuit board. 2. The method of claim 1, wherein the pad on the chip package has a portion with a slit. １１．チップパッケージを印刷回路板上面へ固定する過程は接着剤により行われ る請求の範囲１０記載の方法。11. The process of fixing the chip package to the top surface of the printed circuit board is done using adhesive. 11. The method according to claim 10. １２．印刷回路板およびチップパッケージを清浄にする過程は導体によりパッド 間を電気的に相互接続する過程に先立って行われる請求の範囲１０記載の方法。12. The process of cleaning printed circuit boards and chip packages involves contacting pads with conductors. 11. The method according to claim 10, which is carried out prior to the step of electrically interconnecting between the two. １３．チップパッケージを印刷回路板上面へ固定する過程は接着剤により行われ る請求の範囲１２記載の方法。13. The process of fixing the chip package to the top surface of the printed circuit board is done using adhesive. 13. The method according to claim 12. １４．請求の範囲１記載の方法により製造された物品。14. An article manufactured by the method according to claim 1. １５．請求の範囲１３記載の方法により製造された物品。15. An article manufactured by the method according to claim 13. １６．接続パッドを有する上面を備えた印刷回路板を形成し、その一表面にその 表面の縁部と隣接して配置された接続パッドを有するリード線のないチップパッ ケージを形成し、リード線のないチップパッケージ上の接続パッドが印刷回路板 上の接続パッドと同じ方向を向くようにリード線のないチップパッケージを印刷 回路板上に配置し、印刷回路板上の位置にリード線のないチップパッケージを接 着剤によって固定し、 リード線のないチップパッケージ上のパッドに金属導体を接続し、その同じ導体 を印刷回路板上の対応するパッドに接続し、 リード線のないチップパッケージ上の複数のパッドに対して接続過程を繰返し、 それによってリード線のないチップパッケージの回路が印刷回路板上のパッドに 接続される各過程を含む印刷回路板上でリード線のないチップパッケージを接続 する方法。16. forming a printed circuit board with a top surface having connection pads; Leadless chip pads with connection pads located adjacent to the edges of the surface. Connection pads on a chip package that form a cage and have no leads connect to a printed circuit board Print the chip package without leads to point in the same direction as the connection pads above Place the chip package on the circuit board and connect the chip package without leads to the position on the printed circuit board. Fixed with adhesive, Connect a metal conductor to a pad on a chip package without leads, and connect that same conductor to a pad on a chip package without leads. to the corresponding pad on the printed circuit board, The connection process is repeated for multiple pads on the chip package without lead wires, This allows the leadless chip package circuit to connect to the pads on the printed circuit board. Connecting chip packages without leads on printed circuit boards including each process to be connected how to. １７．電気導体を接続する過程は、超音波溶接、熱圧縮接続、礎接続、ウエッジ 接続および熱音響的接続からなる接続過程の群から選択される請求の範囲１６記 載の方法。17. The process of connecting electrical conductors is ultrasonic welding, thermocompression connection, foundation connection, wedge Claim 16 selected from the group of connection processes consisting of connection and thermoacoustic connection. How to put it on. １８．電気導体の接続は、金、銅、ニッケル、およびアルミニウムからなる群か ら選択された金属線によって行われる請求の範囲１６記載の方法。18. Electrical conductor connections are made from the group consisting of gold, copper, nickel, and aluminum. 17. The method of claim 16, wherein the method is carried out with a metal wire selected from: １９．リード線のないチップパッケージ上のパッドを形成する過程は、パッドが リード線のないチップパッケージの上面および底面の両方に存在するようにパッ ドを形成する過程を含む請求の範囲１６記載の方法。19. The process of forming pads on chip packages without leads is that the pads are The pads should be present on both the top and bottom of the chip package without leads. 17. The method of claim 16, including the step of forming a card. ２０．請求の範囲１９記載の方法により製造された物品。20. An article manufactured by the method according to claim 19. ２１．請求の範囲１６記載の方法により製造された物品。21. An article manufactured by the method according to claim 16. ２２．複数の接続パッドを有する上面を備えた印刷回路板と、上面にその縁部と 隣接して配置された複数の接続パッドを有するリード線のないチップパッケージ と、複数の金属導体とを具備し、 リード線のないチップパッケージの上面の接続パッドおよび前記印刷回路板の上 面の対応するパッドに前記複数の金属導体のそれぞれ一つが接続され、それによ って前記リード線のないチップパッケージが印刷回路板中の回路に電気的に接続 されることを特徴とする物品。22. a printed circuit board with a top surface having a plurality of connection pads and an edge thereof on the top surface; Leadless chip package with multiple adjacent connection pads and a plurality of metal conductors, Connection pads on the top side of the chip package without leads and on the printed circuit board Each one of the plurality of metal conductors is connected to a corresponding pad on the surface, thereby This means that the leadless chip package is electrically connected to the circuit in the printed circuit board. Articles characterized by: ２３．リード線のないチップパッケージは接着剤により印刷回路板上面へ固定さ れる請求の範囲２２記載の物品。23. Chip packages without leads are fixed to the top of the printed circuit board using adhesive. 23. The article according to claim 22. ２４．前記リード線のないチップパッケージ上のパッドは金であり、前記印刷回 路板上のパッドは金、銀、アルミニウムおよび銅からなる群から選択された材料 で構成され、前記電気導体は金、銅、ニッケルおよびアルミニウムからなる群が ら選択された材料で構成されている請求の範囲２２記載の物品。24. The pads on the chip package without leads are gold and the printed circuit The pads on the roadboard are made of a material selected from the group consisting of gold, silver, aluminum and copper. The electrical conductor is made of a group consisting of gold, copper, nickel and aluminum. 23. The article of claim 22, wherein the article is constructed of a material selected from: ２５．前記電気導体は金属線である特許請求の範囲２４記載の物品。25. 25. The article of claim 24, wherein the electrical conductor is a metal wire. ２６．前記電気導体は金属線である特許請求の範囲２２記載の物品。26. 23. The article of claim 22, wherein the electrical conductor is a metal wire.
JP63501263A 1987-01-21 1988-01-21 Method for connecting articles such as chip packages without lead wires Expired - Lifetime JPH0719952B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US571587A 1987-01-21 1987-01-21
US5,715 1987-01-21
PCT/US1988/000146 WO1988005428A1 (en) 1987-01-21 1988-01-21 Method for connecting leadless chip packages and articles

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JPH01501990A true JPH01501990A (en) 1989-07-06
JPH0719952B2 JPH0719952B2 (en) 1995-03-06

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AU (1) AU611127B2 (en)
ES (1) ES2006054A6 (en)
GB (1) GB2208569B (en)
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WO (1) WO1988005428A1 (en)

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US4996629A (en) * 1988-11-14 1991-02-26 International Business Machines Corporation Circuit board with self-supporting connection between sides
GB2283863A (en) * 1993-11-16 1995-05-17 Ibm Direct chip attach module
GB2344550A (en) 1998-12-09 2000-06-14 Ibm Pad design for electronic package
DE10018415C1 (en) 2000-04-03 2001-09-27 Schott Glas Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path
GB2362515B (en) * 2000-04-13 2003-09-24 Zeiss Stiftung Connection of a junction to an electrical conductor track on a plate
US7090098B2 (en) 2004-05-06 2006-08-15 Johnsondiversey, Inc. Metering and dispensing closure
CN102528266B (en) * 2010-12-24 2014-03-05 中国科学院深圳先进技术研究院 Method for welding circuit lead of array element of ultrasonic array ultrasound probe

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JPS53134116A (en) * 1977-04-27 1978-11-22 Toyota Motor Corp Fuel feeder for internal combustion engine
JPS5521148A (en) * 1978-07-31 1980-02-15 Nichicon Capacitor Ltd Method of impregnating electrolytic capacitor
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JPS603141A (en) * 1983-06-20 1985-01-09 Toshiba Corp Circuit board

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ES2006054A6 (en) 1989-04-01
IL85008A0 (en) 1988-06-30
GB2208569B (en) 1991-01-30
GB2208569A (en) 1989-04-05
WO1988005428A1 (en) 1988-07-28
AU611127B2 (en) 1991-06-06
JPH0719952B2 (en) 1995-03-06
GB8821709D0 (en) 1988-11-16
AU1184388A (en) 1988-08-10

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