JPS6365271B2 - - Google Patents
Info
- Publication number
- JPS6365271B2 JPS6365271B2 JP9883082A JP9883082A JPS6365271B2 JP S6365271 B2 JPS6365271 B2 JP S6365271B2 JP 9883082 A JP9883082 A JP 9883082A JP 9883082 A JP9883082 A JP 9883082A JP S6365271 B2 JPS6365271 B2 JP S6365271B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- scanning line
- image signals
- pixels
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000001629 suppression Effects 0.000 claims description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/41—Bandwidth or redundancy reduction
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9883082A JPS58215868A (ja) | 1982-06-09 | 1982-06-09 | フアクシミリ2次元冗長度抑圧符号・復号器用ラインメモリ回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9883082A JPS58215868A (ja) | 1982-06-09 | 1982-06-09 | フアクシミリ2次元冗長度抑圧符号・復号器用ラインメモリ回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58215868A JPS58215868A (ja) | 1983-12-15 |
| JPS6365271B2 true JPS6365271B2 (enrdf_load_stackoverflow) | 1988-12-15 |
Family
ID=14230200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9883082A Granted JPS58215868A (ja) | 1982-06-09 | 1982-06-09 | フアクシミリ2次元冗長度抑圧符号・復号器用ラインメモリ回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58215868A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02138691U (enrdf_load_stackoverflow) * | 1989-04-18 | 1990-11-20 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5958971A (ja) * | 1982-09-29 | 1984-04-04 | Hitachi Ltd | 符号化回路 |
-
1982
- 1982-06-09 JP JP9883082A patent/JPS58215868A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02138691U (enrdf_load_stackoverflow) * | 1989-04-18 | 1990-11-20 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58215868A (ja) | 1983-12-15 |
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