JPS58215868A - フアクシミリ２次元冗長度抑圧符号・復号器用ラインメモリ回路 - Google Patents

フアクシミリ２次元冗長度抑圧符号・復号器用ラインメモリ回路

Info

Publication number
JPS58215868A
JPS58215868A JP9883082A JP9883082A JPS58215868A JP S58215868 A JPS58215868 A JP S58215868A JP 9883082 A JP9883082 A JP 9883082A JP 9883082 A JP9883082 A JP 9883082A JP S58215868 A JPS58215868 A JP S58215868A
Authority
JP
Japan
Prior art keywords
memory
block
line
register
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9883082A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6365271B2 (enrdf_load_stackoverflow
Inventor
Hideaki Kanayama
金山　英明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9883082A priority Critical patent/JPS58215868A/ja
Publication of JPS58215868A publication Critical patent/JPS58215868A/ja
Publication of JPS6365271B2 publication Critical patent/JPS6365271B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/41—Bandwidth or redundancy reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
JP9883082A 1982-06-09 1982-06-09 フアクシミリ２次元冗長度抑圧符号・復号器用ラインメモリ回路 Granted JPS58215868A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9883082A JPS58215868A (ja) 1982-06-09 1982-06-09 フアクシミリ２次元冗長度抑圧符号・復号器用ラインメモリ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9883082A JPS58215868A (ja) 1982-06-09 1982-06-09 フアクシミリ２次元冗長度抑圧符号・復号器用ラインメモリ回路

Publications (2)

Publication Number Publication Date
JPS58215868A true JPS58215868A (ja) 1983-12-15
JPS6365271B2 JPS6365271B2 (enrdf_load_stackoverflow) 1988-12-15

Family

ID=14230200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9883082A Granted JPS58215868A (ja) 1982-06-09 1982-06-09 フアクシミリ２次元冗長度抑圧符号・復号器用ラインメモリ回路

Country Status (1)

Country Link
JP (1) JPS58215868A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958971A (ja) * 1982-09-29 1984-04-04 Hitachi Ltd 符号化回路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02138691U (enrdf_load_stackoverflow) * 1989-04-18 1990-11-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5958971A (ja) * 1982-09-29 1984-04-04 Hitachi Ltd 符号化回路

Also Published As

Publication number Publication date
JPS6365271B2 (enrdf_load_stackoverflow) 1988-12-15

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