JPS6359349U - - Google Patents
Info
- Publication number
- JPS6359349U JPS6359349U JP15320586U JP15320586U JPS6359349U JP S6359349 U JPS6359349 U JP S6359349U JP 15320586 U JP15320586 U JP 15320586U JP 15320586 U JP15320586 U JP 15320586U JP S6359349 U JPS6359349 U JP S6359349U
- Authority
- JP
- Japan
- Prior art keywords
- groove
- insulator
- regions
- drain region
- source region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012212 insulator Substances 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Description
第１図は本考案の一実施例のトランジスタのチ
ヤンネル溝部分の構造を示す説明図、第２図は同
トランジスタの断面図、第３図は従来のＦＥＴの
断面図である。
１……半導体基板、２……単結晶層、３……ソ
ース領域、４……ドレイン領域、９……溝、１０
……酸化膜、１１……ゲート電極、１２……フイ
ールド酸化膜、１３〜１５……コンタクト孔、１
６〜１８……アルミ電極、１９……保護膜。
FIG. 1 is an explanatory diagram showing the structure of a channel groove portion of a transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of the same transistor, and FIG. 3 is a sectional view of a conventional FET. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Single crystal layer, 3... Source region, 4... Drain region, 9... Groove, 10
...Oxide film, 11...Gate electrode, 12...Field oxide film, 13-15...Contact hole, 1
6-18... Aluminum electrode, 19... Protective film.
Claims (1)
に沿つて両領域に接し或いは食い込むように溝を
形成し、該溝内に絶縁物を充填し、該絶縁物を介
してゲート電圧を印加するように構成したことを
特徴とするＭＯＳトランジスタ。 A groove is formed between the source region and the drain region so as to touch or cut into both regions along the direction of both regions, the groove is filled with an insulator, and a gate voltage is applied through the insulator. A MOS transistor characterized in that it is configured as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15320586U JPS6359349U (en) | 1986-10-07 | 1986-10-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15320586U JPS6359349U (en) | 1986-10-07 | 1986-10-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6359349U true JPS6359349U (en) | 1988-04-20 |
Family
ID=31071883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15320586U Pending JPS6359349U (en) | 1986-10-07 | 1986-10-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6359349U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147269A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Field effect transistor |
-
1986
- 1986-10-07 JP JP15320586U patent/JPS6359349U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147269A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Field effect transistor |