JPS635523A - Coating and developing equipment for resist material - Google Patents

Coating and developing equipment for resist material

Info

Publication number
JPS635523A
JPS635523A JP61148792A JP14879286A JPS635523A JP S635523 A JPS635523 A JP S635523A JP 61148792 A JP61148792 A JP 61148792A JP 14879286 A JP14879286 A JP 14879286A JP S635523 A JPS635523 A JP S635523A
Authority
JP
Japan
Prior art keywords
stage
wafer
wafers
coating
resist material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61148792A
Other languages
Japanese (ja)
Other versions
JPH0734426B2 (en
Inventor
Takeo Hashimoto
橋本 武夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61148792A priority Critical patent/JPH0734426B2/en
Publication of JPS635523A publication Critical patent/JPS635523A/en
Publication of JPH0734426B2 publication Critical patent/JPH0734426B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Coating Apparatus (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To reduce the floor space of the title coating and developing equipment by a method wherein at least exceeding two stages out of four component stages i.e. a stage for feeding wafers, a stage for spincoating wafers with resist or developing wafers, a stage for heat treating wafers and a stage for receiving wafers are vertically arranged to be connected in the vertical direction. CONSTITUTION:A coating equipment is arranged with a stage 3a setting up a carrier 2a containing wafers 1 to be coated with resist on the topmost step; a stage 3b equipped with a spincoater 5 on the third step; a stage 3c equipped with a hot plate 6 for prebaking wafers 1 on the second step; and a stage 3d setting up another carrier 2b to receive wafers 1 on the first step. In such a constitution, respective stages are connected in the vertical direction while fork lifts 4a, 4b, 4c are respectively provided between the stage 3a and 3b, 3b and 3c, 3c and 3d in the vertical direction to lower the wafers 1.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置の製造装置、特にレジスト材の塗布
および現像装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device manufacturing apparatus, and particularly to a resist material coating and developing apparatus.

[従来の技術] 従来、レジスト材の塗布および現像装置は第3図に示す
ように、キャリア19aからウェハ18を送り出す部分
23、ウェハにレジストをスピンコートするスピンコー
ター20.レジストが塗布されたウェハに熱処理を施す
ホットプレート21、およびウェハをキャリア19bに
受ける部分24などが横一列に配置され、各構成部間を
ウェハ搬送殿構22a。
[Prior Art] Conventionally, as shown in FIG. 3, a resist material coating and developing apparatus includes a portion 23 for delivering the wafer 18 from a carrier 19a, a spin coater 20 for spin coating the wafer with resist. A hot plate 21 for heat-treating a wafer coated with resist, a portion 24 for receiving the wafer on a carrier 19b, and the like are arranged in a horizontal line, and a wafer transport structure 22a is provided between each component.

22bおよび22cで連結した構造となっていた。It had a structure in which 22b and 22c were connected.

[発明が解決しようとする問題点] 上述した従来のレジスト材の塗布および現像装置は、ウ
ェハを送り出す部分と、ウェハにレジスト材をスピンコ
ートする部分と、ウェハに熱処理を施す部分と、ウェハ
を受ける部分などが横一列に配列された構造となってい
るので、大きな床面積を必要とするという欠点がある。
[Problems to be Solved by the Invention] The conventional resist material coating and developing apparatus described above has a section for sending out the wafer, a section for spin-coating the resist material on the wafer, a section for heat-treating the wafer, and a section for applying the resist material to the wafer. Since it has a structure in which the receiving parts are arranged horizontally in a row, it has the disadvantage of requiring a large floor space.

[発明の従来技術に対する相違点] 上述した従来のレジスト材の塗布および現像装置に対し
、本発明はウェハがキャリアから送り出され塗布おるい
は現像されて再びキャリアに受けられるまでのウェハの
流れを鉛直方向にして装置の床面積を大幅に小さくする
構成に独創的内容を有する。
[Differences between the invention and the prior art] In contrast to the conventional resist material coating and developing apparatus described above, the present invention controls the flow of the wafer from when the wafer is sent out from the carrier, is coated or developed, and is received by the carrier again. The device has an original structure in that it is vertically oriented to significantly reduce the floor space of the device.

[問題点を解決するための手段] 本発明はウェハを送り出す部分と、レジスト材をウェハ
にスピンコート必るいは現像処理を施す部分と、ウェハ
に熱処理を施す部分、およびウェハを受ける部分を有す
るレジスト材の塗布現像装置において、前記4構成部の
少くとも2構成部を上下に配設して鉛直方向に接続した
ことを特徴とするレジスト材の塗布現像装置である。
[Means for Solving the Problems] The present invention has a part for sending out the wafer, a part for spin-coating or developing a resist material on the wafer, a part for heat-treating the wafer, and a part for receiving the wafer. The resist material coating and developing apparatus is characterized in that at least two of the four constituent parts are arranged one above the other and connected in the vertical direction.

[実施例] 以下、本発明の一実施例を図により説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

(実施例1) 第1図(a)は本発明の一実施例の側面図である。(Example 1) FIG. 1(a) is a side view of one embodiment of the present invention.

本塗布機はレジストを塗布するためのウェハ1を入れた
キャリア2aをセットするステージ3aを最上段に、ス
ピンコーター5を装着したステージ3bを3段目に、ウ
ェハのプリベータを行うホットプレート6を装着したス
テージ3Cを2段目に、ウェハを受けるキャリア2bを
セットするステージ3dを1段目にそれぞれ配設し、各
ステージ38〜3dを鉛直方向に接続し、各段の間、す
なわち、ステージ3aと3bの間にウェハを搬送するフ
ォークリフト4a、ステージ3bと3Cの間にウェハを
搬送するフォークリフト4b、およびステージ3Cと3
dの間にウェハを搬送するフォークリフト4Cをそれぞ
れ備えたものでおる。ホットプレート6にはウェハをホ
ットプレートから持ちあげる機構8を装備しである。ま
た第1図(b)に示すように各フォークリフト4a。
This coating machine has a stage 3a on the top stage where a carrier 2a containing a wafer 1 for resist coating is set, a stage 3b equipped with a spin coater 5 on the third stage, and a hot plate 6 for pre-evaluating the wafer. The mounted stage 3C is placed on the second stage, and the stage 3d for setting the carrier 2b for receiving the wafer is placed on the first stage, and the stages 38 to 3d are connected vertically, and between each stage Forklift 4a transports the wafer between stages 3a and 3b, forklift 4b transports the wafer between stages 3b and 3C, and stages 3C and 3.
Each of the forklifts 4C is equipped with a forklift 4C for transporting the wafers between d and d. The hot plate 6 is equipped with a mechanism 8 for lifting the wafer from the hot plate. Moreover, as shown in FIG. 1(b), each forklift 4a.

41)、 4Cに取り付けられたフォーク7a、 7b
、 7cがウェハ1の下にはいり、ウェハの搬送を可能
にする。
41), fork 7a, 7b attached to 4C
, 7c enter under the wafer 1 and enable the wafer to be transported.

実施例において、キャリア2aのなかのウェハ1はフォ
ークリフト4aによってスピンコーター5にセットされ
レジスト材が塗布される。次いで、フォークリフト4b
によってホットプレート6にセットされプリベークされ
た後、フォークリフト4Cによって受けのキャリア2b
へ搬送され、レジスト材の塗布が完了する。
In the embodiment, the wafer 1 in the carrier 2a is set on a spin coater 5 by a forklift 4a, and a resist material is applied thereto. Next, the forklift 4b
After being set on the hot plate 6 and prebaked by the forklift 4C, the receiving carrier 2b is
The resist material is then transported to the substrate, and the coating of the resist material is completed.

(実施例2) 第2図は本発明の実施例2の側面図でおる。本実施例は
レジストの現像装置であり、キャリア10aをセットす
るステージ11aを最上段とし、以下現像装置13を装
着したステージ11b、ボストベータ用のホットプレー
ト14を装着したステージ11cおよび受けのキャリア
10bをセットするステージ11dの順で下段に配設し
、各段の鉛直方向のステージ間にウェハ搬送用の1基の
フォークリフト16を備えたものでおる。
(Embodiment 2) FIG. 2 is a side view of Embodiment 2 of the present invention. This embodiment is a resist developing device, with a stage 11a on which a carrier 10a is set as the top stage, a stage 11b on which a developing device 13 is mounted, a stage 11c on which a hot plate 14 for boost beta is mounted, and a receiving carrier 10b. The stage 11d to be set is arranged at the lower stage in the order in which it is set, and one forklift 16 for transporting the wafer is provided between the stages in the vertical direction of each stage.

本実施例ではフォーク17aと17b1および17bと
17cの間隔は一定であり、ステージ11aとlldに
キャリアを上下に移動させる機構12aおよび12bを
装備し、キャリア内のどの位置のウェハも搬送すること
ができるようになっている。これによりフォークリフト
は1台にできる利点がある。
In this embodiment, the intervals between the forks 17a and 17b1 and 17b and 17c are constant, and the stages 11a and lld are equipped with mechanisms 12a and 12b for moving the carrier up and down, so that the wafer at any position in the carrier can be transported. It is now possible to do so. This has the advantage of allowing only one forklift to be used.

ステージ11aにセットされたキャリア10aのなかの
ウェハはフォークリフト16によって現像装置13にセ
ットされ、次いでホットプレート14に搬送されポスト
ベークされたあと受けのキャリア10bに収納される。
The wafer in the carrier 10a set on the stage 11a is set in the developing device 13 by a forklift 16, then transported to the hot plate 14, post-baked, and then stored in the carrier 10b.

尚各実施例では前段の構成部の下部空スペース内に後段
の構成部を鉛直方向に配列したが、前段の構成部の上部
空スペース内に後段の構成部を配置してこれらを鉛直方
向に配列してもよい。また、実施例では全ての構成部を
鉛直方向に配列したが、おるいは−部の構成部について
、例えば1段目と2段目のみを上下に配設してこれを鉛
直方向に接続してもよい。この場合鉛直方向に配列した
構成部の数だけ床面積分を減少させることが可能となる
In each of the embodiments, the components of the subsequent stage were arranged vertically in the empty space below the component of the previous stage, but the components of the latter stage were arranged in the empty space above the component of the previous stage and arranged vertically May be arranged. In addition, in the example, all the constituent parts were arranged vertically, but for the constituent parts of the - section, for example, only the first and second stages may be arranged vertically and connected in the vertical direction. You can. In this case, it is possible to reduce the floor area by the number of components arranged in the vertical direction.

[発明の効果] 以上説明したように本発明はレジスト材の塗布現像装置
において、ウェハを送り出す部分、レジスト材とウェハ
の密着性向上のための処理を施す部分、レジスト材をウ
ェハにスピンコートあるいは現像する部分、ウェハに熱
処理を施す部分、およびウェハを受ける部分のすべてお
るいは一部を鉛直方向に配置することにより、レジスト
材の塗布用@装置の床面積を非常に小さく抑えることが
できる効果がある。
[Effects of the Invention] As explained above, the present invention provides a coating and developing device for resist material, which includes a section for delivering a wafer, a section for performing treatment to improve the adhesion between the resist material and the wafer, and a section for applying the resist material to the wafer by spin coating or By arranging all or part of the developing area, the wafer heat treatment area, and the wafer receiving area vertically, the floor area of the resist material coating @ equipment can be kept extremely small. effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の一実施例を説明するためのレジ
スト材の塗布装置の側面図、第1図(b)はウェハとウ
ェハ搬送のためのフォークとの関係を示す平面図、第2
図は本発明の一実施例を説明するための現像装置の側面
図、第3図は従来のレジ・スト材の塗布装置を説明する
ための従来の塗布機の側面図である。 1.9・・・ウェハ 2a、 2b、 10a、 10b・・・キャリア3a
、 3b、 3c、 3d、 lla、 11b、 l
lc、 11d ・・・ステージ4a、4b、4C,1
6・・・フォークリフト5・・・スピンコーター 6.14・・・ホットプレート 7a、 7b、 7c、 17a、 17b、 17c
m・・フォーク8.15・・・ウェハ持ち上げ機構 12a、 12b・・・キャリア上下移動機構13・・
・現像装置
FIG. 1(a) is a side view of a resist material coating device for explaining one embodiment of the present invention, and FIG. 1(b) is a plan view showing the relationship between a wafer and a fork for transporting the wafer. Second
FIG. 3 is a side view of a developing device for explaining an embodiment of the present invention, and FIG. 3 is a side view of a conventional coating machine for explaining a conventional resist material coating device. 1.9... Wafer 2a, 2b, 10a, 10b... Carrier 3a
, 3b, 3c, 3d, lla, 11b, l
lc, 11d...Stage 4a, 4b, 4C, 1
6...Forklift 5...Spin coater 6.14...Hot plate 7a, 7b, 7c, 17a, 17b, 17c
m...Fork 8.15...Wafer lifting mechanism 12a, 12b...Carrier vertical movement mechanism 13...
・Developing device

Claims (1)

【特許請求の範囲】[Claims] (1)ウェハを送り出す部分と、レジスト材をウェハに
スピンコートあるいは現像処理を施す部分と、ウェハに
熱処理を施す部分、およびウェハを受ける部分を有する
レジスト材の塗布現像装置において、前記4構成部の少
くとも2構成部以上を上下に配設して鉛直方向に接続し
たことを特徴とするレジスト材の塗布現像装置。
(1) In a resist material coating and developing apparatus having a part for sending out a wafer, a part for spin coating or developing a resist material on the wafer, a part for heat-treating the wafer, and a part for receiving the wafer, the four component parts are as follows: 1. A resist material coating and developing device, characterized in that at least two constituent parts of the above are arranged one above the other and connected in the vertical direction.
JP61148792A 1986-06-25 1986-06-25 Resist material coating and developing device Expired - Lifetime JPH0734426B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61148792A JPH0734426B2 (en) 1986-06-25 1986-06-25 Resist material coating and developing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61148792A JPH0734426B2 (en) 1986-06-25 1986-06-25 Resist material coating and developing device

Publications (2)

Publication Number Publication Date
JPS635523A true JPS635523A (en) 1988-01-11
JPH0734426B2 JPH0734426B2 (en) 1995-04-12

Family

ID=15460799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61148792A Expired - Lifetime JPH0734426B2 (en) 1986-06-25 1986-06-25 Resist material coating and developing device

Country Status (1)

Country Link
JP (1) JPH0734426B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01241840A (en) * 1988-03-24 1989-09-26 Canon Inc Substrate processor
JPH0279413A (en) * 1988-09-14 1990-03-20 Mitsubishi Electric Corp Semiconductor manufacturing device
JPH0261479U (en) * 1988-10-31 1990-05-08
JPH02152251A (en) * 1988-12-03 1990-06-12 Furendotetsuku Kenkyusho:Kk Manufacturing system of vertical-type semiconductor
US5571325A (en) * 1992-12-21 1996-11-05 Dainippon Screen Mfg. Co., Ltd. Subtrate processing apparatus and device for and method of exchanging substrate in substrate processing apparatus
WO2003001579A1 (en) * 2001-06-25 2003-01-03 Tokyo Electron Limited Substrate treating device and substrate treating method
US6511315B2 (en) 2001-01-19 2003-01-28 Dainippon Screen Mfg. Co., Ltd. Substrate processing apparatus
US6790286B2 (en) 2001-01-18 2004-09-14 Dainippon Screen Mfg. Co. Ltd. Substrate processing apparatus
JP2008072140A (en) * 2007-11-21 2008-03-27 Dainippon Screen Mfg Co Ltd Substrate processing apparatus
JP2008229470A (en) * 2007-03-20 2008-10-02 Daifuku Co Ltd Working facility

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177056U (en) * 1974-12-13 1976-06-17
JPS6084819A (en) * 1983-10-14 1985-05-14 Mitsubishi Electric Corp Semiconductor manufacturing apparatus
JPS60182727A (en) * 1984-02-29 1985-09-18 Hitachi Ltd Automatic wafer processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177056U (en) * 1974-12-13 1976-06-17
JPS6084819A (en) * 1983-10-14 1985-05-14 Mitsubishi Electric Corp Semiconductor manufacturing apparatus
JPS60182727A (en) * 1984-02-29 1985-09-18 Hitachi Ltd Automatic wafer processor

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01241840A (en) * 1988-03-24 1989-09-26 Canon Inc Substrate processor
JP2611372B2 (en) * 1988-09-14 1997-05-21 三菱電機株式会社 Semiconductor manufacturing equipment
JPH0279413A (en) * 1988-09-14 1990-03-20 Mitsubishi Electric Corp Semiconductor manufacturing device
JPH0261479U (en) * 1988-10-31 1990-05-08
JPH02152251A (en) * 1988-12-03 1990-06-12 Furendotetsuku Kenkyusho:Kk Manufacturing system of vertical-type semiconductor
JP2592511B2 (en) * 1988-12-03 1997-03-19 株式会社フレンドテック研究所 Vertical semiconductor manufacturing system
US5571325A (en) * 1992-12-21 1996-11-05 Dainippon Screen Mfg. Co., Ltd. Subtrate processing apparatus and device for and method of exchanging substrate in substrate processing apparatus
US6790286B2 (en) 2001-01-18 2004-09-14 Dainippon Screen Mfg. Co. Ltd. Substrate processing apparatus
US6511315B2 (en) 2001-01-19 2003-01-28 Dainippon Screen Mfg. Co., Ltd. Substrate processing apparatus
WO2003001579A1 (en) * 2001-06-25 2003-01-03 Tokyo Electron Limited Substrate treating device and substrate treating method
JP2008229470A (en) * 2007-03-20 2008-10-02 Daifuku Co Ltd Working facility
JP2008072140A (en) * 2007-11-21 2008-03-27 Dainippon Screen Mfg Co Ltd Substrate processing apparatus
JP4499147B2 (en) * 2007-11-21 2010-07-07 大日本スクリーン製造株式会社 Substrate processing equipment

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Publication number Publication date
JPH0734426B2 (en) 1995-04-12

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