JPS6349955A - Memory checking device - Google Patents

Abstract

PURPOSE:To easily check a memory by discriminating whether a ROM is an objective ROM or not in accordance with a result discriminated whether data stored in a specific area of the ROM are specific data or not. CONSTITUTION:An address signal is applied to a memory 1 by an address generating means 2 at the time of turning on a power supply. The address signal is a previously determined specific address value. If the memory 1 is an objective memory, the specific data are stored in a position indicated by the address value, so that the memory 1 outputs storage data corresponding to the address signal applied from the means 2 to a comparing means 3. The comparing means 3 discriminates whether storage data outputted from the memory 1 are the specific data or not. When the storage data are the specific data as the result of discrimination, the memory 1 can be decided as an objective memory.

Description

[Detailed Description of the Invention] [Summary] In order to determine whether the contents stored in a read-only memory are the intended program, the read-only memory must be read by removing it from the processor board, for example. . The present invention determines whether a specific value is stored at a specific address in a read-only memory, and checks whether the read-only memory stores a target program or the like. Misinserted or defective memory can be detected immediately.

[Industrial application field]

The present invention relates to a device having a memory, and more particularly to a memory check device for detecting mounting errors, defects, etc. of the memory.

[Traditional techniques]

With the development of microprocessors, microprocessors have come to be used in various devices.

Microprocessors naturally require programs to control various devices.

Programs for controlling these devices are generally stored in a read-only memory and connected to a pass line of the microprocessor on a board on which the microprocessor is mounted, for example.

In the device using the aforementioned microprocessor,
A program for controlling all purposes corresponds to each device, and the read-only memory that stores this program naturally also corresponds to the device.

However, even if the written contents of the memory storing the above-mentioned program are different or there is a writing error, it cannot be determined from the appearance.

On the other hand, in checking immediately after manufacturing, the manufactured device may not operate as intended. This occurs due to a logic circuit failure such as a disconnection, a failure in the read-only memory due to a failure in the read-only memory, or a failure due to data failure in the read-only memory due to incorrect insertion.

[Problem that the invention seeks to solve]

Conventionally, in order to discover the various failure points mentioned above, the contents of the read-only memory were first checked. This read-only memory check involves removing the read-only memory from, for example, a processor board, and using a device such as a reader to determine whether the stored data is the intended program.

This check has a problem in that it requires a list of data such as programs written in the read-only memory. Furthermore, not only does it require a reading device to read the contents of the read-only memory, but it also requires time to perform this check.

SUMMARY OF THE INVENTION In view of the above conventional drawbacks, it is an object of the present invention to provide a memory check device that checks the memory without removing the memory, reading it with a reading device, or comparing it with source data.

[Means for solving problems]

FIG. 1 is a functional block diagram of the present invention.

1 is a memory to be checked; 2 is an address generation means for adding an address to the memory; 3 is a comparison means for comparing the data stored in the memory 1 corresponding to the address value outputted from the address generation means 2 with a specific value. be.

[For production]

For example, when the power is turned on, an address signal is applied from the address generating means 2 to the memory 1. This address signal is a predetermined specific address value. If memory 1 is the target memory, specific data is stored in the location indicated by this address value, so in response to the address signal applied from address generation means 2, memory 1 will store the corresponding stored data. is output to the comparison means 3. The comparison means 3 determines whether the stored data output from the memory 1 is specific data. If the stored data is specific data in the above determination, it can be determined that the memory is the target memory. Further, if the data differs from specific data, it can be determined that the memory is not the intended memory, or the memory is defective, or there is defective writing.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

The address generator (ASET) 11 is a circuit that outputs an address signal 5ADR of a specific value, and the address signal 5ADR is input to the multiplexer (MPXI) 12.
join. Further, 11 of the multiplexer 12 is connected to an address line of a microprocessor (CPU) (not shown), and an address signal ADR1 of the processor is applied thereto.

The multiplexer 12 receives these two address signals 5ADR.
.

This is a circuit that selects ADR1.

On the other hand, "1" is applied to the input I4 of the multiplexer (MPX2) 13 from a circuit not shown, and the read control line RDCI of the microprocessor is connected to the input I3. The control circuit (CONT) 4 is a read-only memory 5
This circuit outputs various control signals for check control of the multiplexer 12.
A switching signal CHE of "0" is output to the 13 selection terminals 5ELI and 5EL2. When this switching signal CHE is "0", multiplexers 12 and 13 are operated manually by I+,
A signal applied to Tz is selected and output. Multiplexer 1
The output of 2.13 is applied to the read-only memory (ROM) address input ADR and the read control manual RDC. Therefore, when the switching signal CHE is "0", the multiplexers 12 and 13 described above are switched to the processor (CP
Address signal ADR1 and read control signal RDCI from U) are input.

The data output DO of the read-only memory 5 is connected to a data bus of a processor (CPU) not shown, and data corresponding to an address signal applied from the processor (CPU) is output via this data bus. .

For example, if a program is stored in the read-only memory 5, the processor sequentially reads the contents of the read-only memory and executes it. That is, the control circuit 4
When the switching signal CHE output from the multiplexer 12.13 is "0", the multiplexer 12.13 selects the signal from the processor (CPU), resulting in the operation of a read-only memory in a general processor circuit.

On the other hand, the control circuit 4 is supplied with a cent signal RESET. The reset signal changes to the second level when the power is turned on or when a manual reset switch (not shown) is pressed.
1” as shown in Figure +a).This reset signal R
When ESET becomes "1", the control circuit 4 sets the aforementioned switching signal CHE to "1" (FIG. 3(e)). Switching signal C
When HE is “0”, multiplexer 1
2.13 selects the address signal ADR1 and the read control signal RDC1 and outputs them to the read-only memory 5, but when the switching signal CHE is "1", the address signal 5ADR output from the address generator 11 respectively
and 1" and add it to read-only memory 5 (3rd
Figures (bl, (cl)).When "l" is added to the read control manual RDC, the read-only memory 5 is activated by the multiplexer 2.
Data at the storage location indicated by the input address signal ADR2 (address signal S ADR is selected at this time, FIG. 3(b)) is output. Read only memory 5
Data of a specific value is stored in the storage location indicated by the aforementioned address signal 5ADR. The data output of the read-only memory 5 is connected to the data bus of the processor CPU, and is also connected to a comparison circuit (CMP) 6.

The data generator (DSET) 7 is a circuit that outputs the same data as the data (FIG. 3(d)) at the specific position of the read-only memory, that is, the position indicated by the address signal 5ADR, and this output is also output from the comparison circuit. It has joined 6.

The comparison circuit 6 is a circuit that compares the two pieces of data described above, and sets the error signal ERR1 to "1" when they do not match, and sets it to "0" when they match.

For example, when the read-only memory 5 stores a target program, etc., when the address signal 5ADR is applied, the target data is output from the read-only memory 5, but the error signal ERR1 is output from the comparison circuit 6. is “0”
is output as

However, if the target data is not stored, the data generator 7 outputs an error signal ERR1 of ``1''.
”.Then, this error signal ERRI
joins AND gate 8.

The control circuit 4 sets the switching signal CHE to "1" and then sets the gate signal DCH to "1" (FIG. 3 ()).

Since the gate signal DCH is added to the AND gate,
When this signal becomes "1", the level of the error signal ERRI output from the comparator circuit 6 is output from the AND gate. That is, when the data 5DATA output from the data generator and the data output from the read-only memory 5 do not match in the comparator circuit 6, the error signal ERR1 becomes "1" and the error signal ERR2 is generated by the AND gate. If they match, "1" is output (FIG. 3 fh)), and when they match, "0" is output.

The output of the AND gate is connected to the cent terminal S of the flip-flop (FF) 9. Then, the lamp clear signal LCLR output from the control circuit 4 is applied to the reset terminal R.
Participating in Reset terminal R of flip-flop 9
The lamp clear signal LCLR applied to the gate signal becomes "1" before the gate signal DCH becomes "1" as shown in FIG. 3(g).
Therefore, it becomes "0" at the same time as DCH becomes "1".

Therefore, since the clip-flop 9 is reset before the comparison result of the comparator circuit 6 is added via the AND gate 8, when the error signal ERR1 is "1", the gate signal DCH is "1" and the output of the AND gate 8 is Output ERR2 is 1
'' and sets the flip-flop 9. Furthermore, when the error signal ERR1 is "0", the gate signal DCH
Even if becomes "1", the output ERR2 of the AND gate 8 is '
0'', the clip-flop 9 is not set.

The output Q (ERR3) of the flip-flop 9 is output from the amplifier (A
MP) 10, and the output of the amplifier 10 is connected to a lamp 14 whose one end is grounded.

Clip-flop 9 outputs Q (ERR
3. When "1" is reset again in FIG. 3(1)), "O" is output. Also, when the output Q (ERR3) of the flip-flop 9 is "1", the amplifier 10 outputs the lamp 14.
is turned on, and remains off when it is 0''. Therefore, the comparison result in the comparator circuit 6, that is, the error signal ERR
When I is "l", the clip-flop 9 is set and the lamp is turned on. Conversely, when the error signal ERR1 is "0", the lamp remains off.

The error signal is "1" when the results in the comparison circuit 6 do not match, that is, when the contents of the read-only memory 5 are not the desired data, so when the lamp lights up, it indicates that the read-only memory was inserted incorrectly. This indicates that a write error has occurred.

To summarize the above operations, the control circuit 4 starts checking the read-only memory 5 immediately after the reset signal "1" is applied, and reads the contents of the read-only memory 5 specified by the target address signal 5ADR. . Then, it is compared with the output data 5DATA of the data generator 7, and if it is negative, the clip-flop 9 remains in the reset state and the lamp does not light up. When they do not match, the flip-flop 9 is set and the lamp is lit.

The present invention has been described in detail using embodiments of the present invention, but the present invention is not limited to read-only memories in microprocessors, but can also be applied to circuits using read-only memories, programmable logic arrays PLA, etc. can be used.

Further, it can be similarly used by comparing the start vector address read out when the microprocessor executes execution after reset release, the command read out upon start of execution, etc. using a comparison circuit.

〔Effect of the invention〕

As described above, the present invention determines whether the read-only memory is a target read-only memory depending on whether or not the data stored in a specific area of the read-only memory is specific data. Accordingly, it is possible to obtain a memory check device that checks the memory without removing the memory, reading the data continuously in a reading device, or comparing the data with source data.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of the present invention, FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 3(a)
~ (11 is a timing chart diagram of an embodiment of the present invention. 1... Memory, 2... Address generation means, 3... Comparison means. Patent applicant: Fujitsu Limited Procedural Correction Interpretation) November 27, 1986

Claims (1)

[Claims] Address generating means (2) for adding a specific address value to the memory (1), and storing data in the memory (1) corresponding to the address value output from the address generating means (2). A memory check device further comprising comparison means (3) for comparing with specific data.