JPH0264726A - Information processor to connect external memory device - Google Patents

Abstract

PURPOSE:To improve operability and to prevent the generation of malfunction even when an external memory device is inserted imperfectly into an information processor by providing an external memory detecting means, a signal generating means, a control means, etc. CONSTITUTION:When an external memory device 10 is inserted into an information processor 20, the device 20 inputs detection signals CD0 and CD1 generated from signal generating means 12a and 12b of the device 10 and detects the condition of the insertion through an external memory detecting means 23. When it is judged that the device 10 is inserted normally, an initializing operation is performed by a control means 26. When the device 10 is pulled out of the device 20, the signals CD0 and CD1 from the device 10 are not detected through the means 23, and when it is judged that the device 10 is pulled out, the stop operation is performed by the means 26. By arranging the means 12a and 12b in both end parts of an input/output terminal 11, the condition of the connection of the device 20 with the device 10 can be surely detected, the generation of the malfunction is prevented, the operation from the insertion to the pulling-out is lightened and the operability can be improved.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an information processing device that uses an external memory device such as a memory card or a ROM cartridge, and particularly relates to an information processing device that uses an external memory device such as a memory card or a ROM cartridge. The present invention relates to an information processing device to which a detectable external memory device is connected.

(Prior Art) As a portable external storage medium (external memory device in the present invention) for an information processing device, for example, a card-sized memory card on which a semiconductor memory element is mounted has come to be used. In conventional information processing devices, there was no means for detecting whether an external memory device was inserted into the information processing device.

(Problem to be Solved by the Invention) The conventional information processing device connected to the external memory device described above does not have a means for detecting whether or not the external memory device is inserted into the information processing device. If the device is not inserted correctly into the information processing device (if the external memory device is inserted at an angle to the information processing device), the information processing device and external memory device are not connected properly and processing cannot be performed correctly. That means,
Furthermore, even if the external memory device is correctly inserted into the information processing device, some activation operation may be required, and if the external memory device is removed from the information processing device,
The information processing device had no means of knowing that the external memory device had been removed.

The present invention has been made in view of the above-mentioned points, and by detecting the connection state between an information processing device and an external memory device, it is possible to prevent malfunction of the device based on information when the external memory device is inserted, and also prevent the device from malfunctioning. To provide an information processing device to which an external memory device is connected, which greatly improves operability by reducing operations for a person using the device from the time the memory device is normally inserted to the time the external memory device is removed. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) An external memory device having a semiconductor memory element capable of reading/writing data, and an information processing device that connects and uses this external memory device as an auxiliary storage medium, The information processing is performed using external memory detection means for detecting a connection state between the external memory device and the information processing device, and detection information indicating the connection state between the external memory device and the information processing device detected by the external memory detection means. An information processing device to which an external memory device is connected, characterized by comprising: control means for controlling the device.

In an external memory device having a semiconductor memory element capable of reading/writing data, and in an information processing device that connects and uses this external memory device as an auxiliary storage medium, data input/output terminals of the external memory device are connected at intervals from each other. When both the detection signals are detected, the information processing device receives the external memory from the external memory device, and the external memory device and the information processing device are connected to each other. External memory detection means for determining that the external memory device is not inserted into the information processing device when it is determined that the device has been inserted and at least one of the detection signals is not detected. An information processing device to which an external memory device is connected, characterized by:

In an external memory device having a semiconductor memory element capable of reading/writing data, and in an information processing device that connects and uses this external memory device as an auxiliary storage medium, data input/output terminals of the external memory device are connected at intervals from each other. signal generating means arranged so as to maintain the detection signals, and external memory detecting means connected to the external memory device and the information processing device and detecting both the detection signals;
and control means for detecting the inserted state and removed state of the external memory device by the external memory detection means, and performs an initialization operation or a stop operation for the information processing device based on this detection information. An information processing device to which a memory device is connected.

(Function) In the device configured as described above, when an external memory device is inserted into an information processing device, the information processing device detects a detection signal generated from the external memory device, and the detection signal is inserted. When the state is detected, it is determined that the external memory has been inserted in a normal state, and an initialization operation is performed;
Further, when the external memory device is removed from the information processing device, detecting that the detection signal from the external memory device is not detected and the state changes from the inserted state to the removed state;
It becomes possible to perform a stop operation by determining that the external memory device has been removed.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an external memory device and an information processing device according to an embodiment of the present invention. The external memory device 1o is provided with an input/output terminal 11 for inputting and outputting data, and a semiconductor memory element 13 that can read/write data via this input/output terminal 11 is arranged. Signal generating means 12a and 12b for generating detection signals are arranged at both ends of the data input/output terminal 11. On the other hand, the information processing device 2o includes an accepting means 21 that accepts the external memory device 10, an external memory detecting means 23 that detects the acceptance state of the external memory device 10, and a control that operates according to the detection result of the external memory detecting means 23. Means 26 are provided. In the receiving means 21 of the information processing device 20, a pull-up resistor 31aSb and a Schmitt trigger inverter (hereinafter referred to as 5TINV) 32aSb are provided at positions that receive the detection signal output from the signal generating means 12aSb. The detection signal is sent to external memory detection means 23 via receiving means 21 . The external memory detection means 23 is composed of an AND gate 33, an insertion detection means 24 and a removal detection means 25 connected to the AND gate 33. Insertion detection means 24
is an open collector gate (hereinafter referred to as OCG)
34, a resistor 35, and a capacitor 36. Further, the removal detection means 25 includes an inverter 37. These insertion detection means 24 and removal detection means 25 are each connected to a control means 26. Further, in the external memory detection means 23, the AND gate 33 outputs a DET signal 38, the insertion detection means 24 outputs a RESET signal 39, and the removal detection means 25 outputs a INT signal 40.

The following signals are exchanged between the external memory device 10 and the information processing device 20. External memory device 10
An address signal used when addressing the semiconductor memory element 13 in the memory. In this embodiment, a 16-bit address space is assumed, and 64 bytes can be directly addressed. Bidirectional data bus. In this example, 8
It's a bit of a bit of a bit of a bit of a bit of a bit of a bit. Data is transferred between the external memory device 10 and the information processing device 20 via this bidirectional data bus. When the read control signal becomes active, data can be read from the semiconductor memory element 13 in the external memory device 10 to the information processing device 20. When the write control signal becomes active, data from the information processing device 20 can be written to the semiconductor memory element 13 in the external memory device 10. When the card select signal C8 is activated, the information processing device 20 can access the external memory device 1o. An external memory device 10 is provided in the information processing device 2o.
A detection signal generated from the external memory device 1o when the external memory device 1o is inserted. Power supply to external memory device 1o. ground wire.

Next, the operation of one embodiment of the present invention will be explained in FIGS. 2, 3, and 4.
This will be explained with reference to the drawings and FIG.

FIG. 2 shows a state in which the external memory device 10 is inserted into the information processing device 20, and a state in which the external memory device 10 is inserted into the information processing device 20.
The output DET signal 3 of the AND gate 33 with the
8 is a waveform diagram showing the states of the output RESET signal 39 of the insertion detection means 24 and the output INT signal 40 of the removal detection means 25.

FIG. 3 is a flowchart showing a series of steps when handling the external memory device 10. FIG. 4 is a flowchart showing the operation of the control means 26 when the insertion detection means 24 detects acceptance of the external memory device 10. FIG. 5 is a flowchart showing the operation of the control means 26 when the removal detection means 25 detects removal of the external memory device 10.

When the external memory device 10 is not inserted into the information processing device 20, the outputs of the 5TINV32aSb in the receiving means 21 are each held at a low level. Also,
At this time, the DET signal 38 and the RESET signal 39 are held at low level, and the INT signal 40 is held at high level.

The control device 26 also receives a RESET signal 39 or an INT signal.
It operates only when the signal 40 changes from low level to high level.

Here, a case where both the detection signals CDO and CDI are received by the receiving means 21 and a case other than this will be explained.

First, a case will be described in which both the detection signals CDO and CD1 are received by the receiving means. When the detection signals CDO and CDI are supplied to the input sides of the 5TINVs 32a and 32b, the outputs of the 5TINVs 32a and 32b change from low level to high level. The output of 5TINV32aSb that has changed to high level is input to the AND gate 33. Then, the output DET signal 38 of the AND gate 33 becomes high level (FIG. 2, A).

The DET signal 38 is manually input to the insertion detection means 24 and the removal detection means 25, respectively. The signal input to the insertion detection means 24 passes through the 0CG34, and then rises from a low level to a high level by applying time IL'l t 1 through a resistor 35 and a capacitor 36 (FIG. 2, A-B).
, becomes the output RESET signal 39 of the insertion detection means 24.

By delaying the rise time, time is secured until the operation of the control means 26 becomes stable. The control means 26 performs an initialization operation in response to the change in the output RESET signal 39 of the insertion detection means 24 from low level to high level. As the initialization operation of the control means 26, the following processing is performed. First, the hardware in the control means 26 is initialized (FIG. 4, Sl).

Next, a program is executed from a specific address of a ROM (not shown) in the control means 26 (FIG. 4, S2).

Then, the program stored in the semiconductor memory element 13 in the external memory device 10 is executed (FIG. 4, S3
).

On the other hand, the AND gate 33 manually operated by the removal detection means 25
The signal is output as an INT signal 40 via the inverter 37, and at this time, the INT signal 40 changes from high level to low level. In this case, no stopping action is performed (
Figure 2, A).

Next, a case where one or both of the detection signals CD01CDI is not received by the receiving means 21 will be described. In this state, the signal is output to the AND gate 33.
Even if the output DET signal 38 is inputted to the output signal 38, the output DET signal 38 remains at a low level. The DET signal 38 is input to the insertion detection means 24 and the removal detection means 25, respectively. Even if the signal input to the insertion detection means 24 passes through the internal circuit, the output RESET signal 39 of the insertion detection means 24 remains at a low level, and the control means 26 does not input the RESET signal 39 even if the RESET signal 39 is input. Since there is no change in the signal, no initialization operation is performed. In addition, the signal manually inputted to the removal detection means 25 is
It becomes high level by INV37. However, the output INT signal 40 of the removal detection means 25 remains at a high level, and the control means 26 does not perform a stopping operation even if the INT signal 40 is input. In other words, when the receiving means 21 cannot receive both of the detection signals CD05CDI, such as when the receiving means 21 cannot receive the detection signals CD05CDI, such as when the receiving means 21 is not inserted properly, the information processing apparatus does not operate.

Next, a case where the external memory device 10 is removed from the information processing device 20 will be described. In this case, in a state where the external memory device 10 is normally inserted into the information processing device 20 (the state here means that both signals of the detection signal CD0SCDI are received by the receiving means 21), the external memory device 10
0 is extracted from the information processing device 20. The signals in the normally inserted state are the detection signals CDO and CDI at high level, the DET signal 38 and the RESET signal 3.
9 is also held at high level, and the INT signal 40 is held at low level. From this state, external memory device 1
0 from the information processing device 20, first the detection signal C
D01CDI is no longer supplied to the receiving means 21. In response to this, the outputs of the 5TINVs 32a and 32b of the receiving means output 21 both change from high level to low level, and these signals are input to the external memory detecting means 23.

5TINV32a input to external memory detection means 23
, b are sent to an AND gate 33. AN
The DET signal 38, which is the output of the D gate 33, changes from high level to low level (FIG. 2, C). The DET signal 38 is sent to the insertion detection means 24 and the removal detection means 25. DET signal 3 input to insertion detection means 24
8 becomes an output RESET signal 39 through an internal circuit.

(7) The RESET signal 39 changes from high level to low level over time t2 (FIG. 2, C to D).

In the control device 26, even if this RESET signal 39 is received, since the change in the RESET signal 39 is from a high level to a low level, no initialization operation is performed. On the other hand, the output INT signal 40 of the signal input to the removal detection means 25 is changed from low level to high level by the inverter 37. Upon receiving this INT signal, the control means 26 performs a stopping operation. The control means 26 stops execution of the program in the external memory device 10 in response to the change of the INT signal 40 from low level to high level (FIG. 5, Sl
).

In this embodiment, the external memory device 10 may be in the form of a ROM in which a program is pre-loaded, or may be in the form of a RAM for storing data, as long as it is suitable for the purpose of use. Furthermore, the connection portion between the external memory device 10 and the information processing device 20 (the
, the external memory receiving means 21) may be of a connector type, a contact type, or the like.

As described above, in the present invention, when the external memory device 10 is inserted into the information processing device 20, the information processing device 20 detects the detection signal CD01CDI generated from the signal generation means 12a, b of the external memory device 10, and When the insertion state is detected by receiving a detection signal, it is determined that the external memory device 10 is inserted in a normal state and initialization operation is performed. It is possible to detect that the detection signal from the external memory device 10 has not been detected and change from the inserted state to the uninserted state, determine that the external memory device 10 has been removed, and perform a stop operation.

In addition, the signal generating means 12 a s b are connected to the input/output terminal 11
By arranging the external memory device 10 at both ends of the information processing device 2o, the connection state between the information processing device 20 and the external memory device 10 can be reliably detected. This can prevent malfunctions that may occur.

[Effects of the Invention] As described above, the present invention detects that the external memory device is incomplete in the information processing device by the detection signal generated from the signal generating means arranged at a distance from each other on the input/output means of the external memory device. No malfunction occurs even when the external memory device is inserted into the computer, and the operation of the track that must be performed when the external memory device is inserted correctly can be omitted, and the information processing device can now detect when the external memory device has been removed from the information processing device. . In this way, the operational burden on the user can be reduced, and it is also possible to measure the stability of an information processing device that uses an external memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an external memory device and an information processing device according to an embodiment of the present invention, and FIG. 2 shows a case where the external memory device is inserted into the information processing device and an external memory from the information processing device. A waveform diagram showing the states of the DET signal, RESET signal, and INT signal when the device 1° is removed,
FIG. 3 is a flowchart showing a series of steps when handling an external memory device, FIG. 4 is a flowchart showing the operation of the control means when the insertion detection means detects acceptance of the external memory device, and FIG. The figure is a flowchart showing the operation of the control means when the removal detection means detects removal of the external memory device. 10... External memory device, 11... Input/output terminal, 1
2... Signal generating means, 13... Semiconductor memory element,
20... Information processing device, 21... Acceptance means, 23.
...External memory detection means, 24...Insertion detection means, 2
5... Removal detection means, 26... Control means, 38...
・DET signal, 39... RESET signal, 40... Bow NT signal

Claims (3)

[Claims] (1) In an information processing device that connects and uses an external memory device having a semiconductor memory element that can read/write data and this external memory device as an auxiliary storage medium, the connection between the external memory device and the information processing device External memory detection means detects a state, and detection information indicating a connection state between the external memory device and the information processing device detected by the external memory detection means,
An information processing device to which an external memory device is connected, comprising: a control means for controlling the information processing device; (2) In an external memory device having a semiconductor memory element capable of reading/writing data, and an information processing device that connects and uses this external memory device as an auxiliary storage medium, on a data input/output terminal of the external memory device. , signal generating means arranged at a distance from each other and generating detection signals respectively; and a signal generating means that generates a detection signal respectively when the external memory device and the information processing device are connected to each other, when both the detection signals are detected, the information processing device external memory detection means that determines that the external memory device is inserted, and determines that the external memory device is not inserted into the information processing device when at least one of the detection signals is not detected; An information processing apparatus to which an external memory device according to claim 1 is connected. (3) An external memory device having a semiconductor memory element capable of reading/writing data, and an information processing device that connects and uses this external memory device as an auxiliary storage medium, on a data input/output terminal of the external memory device. , signal generating means arranged at intervals and generating detection signals respectively; external memory detecting means connected to the external memory device and the information processing device and detecting both the detection signals; and the external memory detecting means. Claims further comprising control means for detecting the insertion state and removal state of the external memory device by means of means, and performing an initialization operation or a stop operation of the information processing device based on the detected information. An information processing device to which the external memory device according to item 1 is connected.