JP2002049504A - System including flash memory, flash memory built-in lsi, and debugging system using them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash memory built-in LSI which eliminates the need to specially develop an evaluation chip for program debugging and can verify even the operation that an emulator hardly reproduces faithfully in debugging. SOLUTION: A memory interface 10 detects which mode the system is in; a real operation mode or an operation mode wherein the emulator is connected. When the emulator is connected, connection to a bus 408 is switched to an internal bus 404 or external bus 402 by the object memory control signal 406 outputted from the object memory control circuit 120.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a system including a flash memory for storing a program code or a program code and a data code, an LSI with a built-in flash memory, and more particularly to a debug system for debugging a program code.

[0002]

2. Description of the Related Art A flash memory used in a system having a CPU often stores program codes used in the system. Further, with an increase in the capacity of the flash memory and an increase in the guaranteed number of rewrites, the number of cases in which data codes are stored together with program codes in the flash memory is increasing.

Conventionally, an LSI having a built-in flash memory for storing a program code has been used to debug a program using an evaluation chip dedicated to debugging different from an actual product.

FIG. 7A shows an example of an actual product.
(B) shows an example of an evaluation chip. FIG.
As shown in (a), in a real product, a flash memory is built in together with a CPU and its peripheral circuits (SRAM, random logic (DRAM), etc.) and connected by an internal bus. On the other hand, in the evaluation chip, as shown in FIG. 7B, the flash memory is not built in. Instead, signals such as address signals, data signals, and control signals which are originally connected to the flash memory are transmitted. Output as an external terminal. That is, in the evaluation chip, an emulator that performs the operation of the flash memory through a signal output as an external terminal is connected, and the operation of the built-in flash memory is realized by the emulator. Further, the emulator has a program debugging function, and debugging is performed by the emulator.

A debugging system using the above evaluation chip is disclosed in, for example, JP-A-11-282.
No. 712. The configuration of the debugging system disclosed in JP-A-11-282712 will be described with reference to FIG. In this debug system, the emulator main body 2 is connected to a target substrate 4 which is a substrate on which a flash memory is actually provided. Also, the emulator body 2
It is also connected to the host computer 6. The emulator body 2 includes a host interface (HIF) 10, a CPU
, A control program memory 14, an emulation memory 1 comprising a RAM
6, a flash memory command analysis unit 18, an electrical emulation unit 20, and a buffer 22.

The emulation memory 16 is for storing basically the same contents as the flash memory mounted on the target substrate 4, and the control program memory 14 is for storing the program executed by the controller 12. belongs to. The flash memory command analysis unit 18 is a circuit for detecting a flash memory command issued from the target substrate 4, and includes a logical operation element and the like for realizing processing at a speed close to the actual operation inside the flash memory. It is configured in hardware by using. The electrical characteristic emulation unit 20
For example, it is a circuit for realizing the same impedance as each terminal of the flash memory. The host interface 10 connects the host computer 6 and the controller 12. The controller 12 executes the program stored in the control program memory 14, communicates with the host computer 6 via the host interface 10, and downloads the program to the emulation memory 16. The buffer 22 controls access to the emulation memory 16.

[0007] A target bus 24 extends from the emulator body 2. As the target bus 24, for example, a flexible cable can be used so as to be easily connected to the target substrate 4. The target board 4 side of the target bus 24 is connected to a flash memory emulator adapter 26. Although the flash memory emulator adapter 26 is actually arranged (inserted) on the probe 28, it is shifted in FIG. 8 for easy understanding of the configuration. The flash memory emulator adapter 26 and the mounting position of the flash memory on the target substrate 4
Connected through. Thus, the emulator main body 2 and the target substrate 4 are connected. When the emulator main body 2 is connected, no actual flash memory is arranged at the flash memory mounting position on the target substrate 4.

The target substrate 4 is a substrate used for an actual product such as an engine control circuit of an automobile or a control circuit of a video camera.
(Target CPU) 30. In the actual product,
The target CPU 30 reads and executes a program from a flash memory arranged on the substrate,
In addition, operations such as block erase and writing are performed on the flash memory. The host computer 6
Controller 12 via host interface 10
Is connected to and downloads data.

According to this conventional technique, it is possible to emulate a command sequence unique to a flash memory by treating the emulation memory as if it were a flash memory.

[0010]

As described above, in the above-described prior art, an evaluation chip different from an actual product is separately developed only for debugging a program in an LSI having a built-in flash memory for storing a program code. There is a need to. Therefore, development man-hours /
An increase in development cost leads to an increase in the cost of the LSI, and when a defect is found in the LSI with a built-in flash memory, the evaluation chip has to be corrected.

In the prior art, the flash memory is replaced with an emulation memory, and although the electric characteristic emulation section 20 exists, the electric characteristics of the flash memory mounted on the product, particularly, the writing (command issuing) operation. There is a problem that the AC characteristics are different from those at the time. Specifically, since the AC characteristics of the flash memory depend on the block size, the flash memories having different block sizes have different AC characteristics. Further, even in the same flash memory, the time required for the verify (verification) operation after writing differs depending on the state of aging or the like, so that the AC characteristics are not always the same. Since the AC characteristics differ depending on various conditions as described above, it has been difficult to faithfully reproduce the AC characteristics of the flash memory by the emulator.

Further, since the command set and command sequence of the flash memory differ for each flash memory used in general, an emulator can be developed for each command set or command sequence, or can be used for general purposes. To do
It was necessary to provide a function corresponding to a plurality of different command sets and command sequences. For this reason, it was difficult to realize an inexpensive and highly versatile emulator. As described above, it is difficult to faithfully reproduce the operation of the flash memory actually used including the AC characteristics by the emulator, and it is very difficult to perform a complete operation verification.

The present invention has been made to solve such problems of the prior art, and eliminates the need to develop an evaluation chip different from an actual product only for debugging a program, and at the time of debugging. For operations that are difficult to reproduce faithfully with the emulator,
A system including a flash memory and a built-in flash memory capable of eliminating a mismatch between an actual flash memory including AC characteristics and an emulator by accessing an actually mounted flash memory and enabling complete operation verification An object of the present invention is to provide an LSI and a debugging system using them.

[0014]

A system including a flash memory according to the present invention can substitute a memory operation of the flash memory in a system including a flash memory for storing a program code or a program code and a data code. An external bus connected to the emulator; an operation mode detecting means for detecting whether the system is in an actual operation mode or an emulation operation mode to which the emulator is connected; and an emulation operation mode by the operation mode detection means. A memory switching means for switching whether to access the flash memory or to access the emulation memory in the emulator when it is detected that the above object is achieved.

An LSI with a built-in flash memory according to the present invention comprises:
LS with built-in flash memory for storing program code or program code and data code
I, an external bus connected to an emulator capable of acting as a memory for the flash memory, and an operation mode detecting means for detecting whether the system is in an actual operation mode or an emulation operation mode to which the emulator is connected And when the operation mode detecting means detects that the emulation operation mode is selected, the flash memory is accessed by switching between an internal bus connected to the flash memory and an external bus connected to the emulator, or A target memory switching means for switching whether to access the emulation memory in the emulator, thereby achieving the above object.

According to the above configuration, the actually used flash memory mapped in the same memory space and the emulation memory in the emulator are determined according to whether the operation mode is the actual operation mode or the emulation operation mode. Further, switching can be performed depending on whether an access target to the memory is a program code which is a program executed by the CPU or a data code such as sound or image. Therefore, the actual operation and the emulation operation can be realized on the same chip, and it is not necessary to separately develop an evaluation chip different from an actual product for debugging a program.

A debug system of the present invention comprises a system including the flash memory of the present invention or an LSI with a built-in flash memory of the present invention, and an emulator capable of acting as a memory for the flash memory and having a program debugging function. Thus, the above object is achieved.

According to the above configuration, at the time of debugging using the emulator, operations that are difficult to faithfully reproduce with the emulator can be performed by accessing the flash memory actually used. Therefore, AC characteristics, etc.
Complete operation verification can be performed while avoiding mismatch between the actual flash memory and the emulator.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of an LSI with a built-in flash memory according to an embodiment of the present invention. This configuration is obtained by adding a memory interface 110 and a target memory 120 to an ordinary flash memory built-in LSI.

In FIG. 1, a flash memory built-in LSI 100 includes a CPU 1 for detecting an operation mode.
02, a flash memory 112 for storing program codes and data codes, a serial interface 114 for downloading data to the flash memory 112, and an input / output port connected to a target system (a target controlled by the flash memory built-in LSI 100) 116, S which is a peripheral circuit of the CPU
It comprises a RAM 118, a target memory control circuit 120 including a target memory control register 104 for controlling switching of an access target memory, and a memory interface 110 for detecting an operation mode of the LSI 100 with built-in flash memory and switching the access target memory. In FIG. 1, reference numeral 402 denotes an external bus connected to the emulator, and an operation mode detection signal 402-
a, a CPU control signal 402-b, an emulation memory address bus 402-c, an emulation memory data bus 402-d, and an emulation memory access signal 402-e. Also, 40
Reference numeral 4 denotes an internal bus connected to the flash memory, which corresponds to a flash memory address bus 404-a, a flash memory data bus 404-b, and a flash memory access signal 404-c, which will be described later. Also, 40
Reference numeral 6 denotes a target memory switching control signal output from the target memory control circuit 120 in accordance with the value stored in the target memory control register 104. Reference numeral 408 denotes a bus for connecting each component of the flash memory built-in LSI, and includes an operation mode detection signal 408-a, which will be described later, and a CPU.
Control signal 408-b, memory address signal 4
08-c, the memory data signal 408-d, and the memory access signal.

This LSI 100 with built-in flash memory
Unlike the conventional evaluation chip used for debugging a program, since the flash memory 112 is built in, the same LSI can be used in an actual product.

FIG. 2 is a diagram for explaining the structure of the memory interface 110 in FIG. 1 in more detail. In FIG. 2, reference numeral 406 denotes a target memory switching control signal for the memory interface 110.

The CPUs 402-a and 408-a
2 is an operation mode detection signal used to notify the emulator connection to the memory interface 1 based on the operation mode detection signal 402-a input from the outside.
Based on the operation mode detection signal 408-a generated by the CPU 10, the CPU 102 detects whether or not the emulator is connected. When the emulator is not connected, the operation mode detection signal is fixed to one of the low level and the high level in the memory interface 110. For example, if the actual operation mode is set when the operation mode detection signal is at the low level, when the CPU 102 detects the low level and recognizes that the operation mode is the actual operation mode, the flash memory 112 is selected as the access target memory. Thus, the target memory switching control signal 406 is fixed for the target memory control circuit 120. On the other hand, when the emulator is connected, the operation mode detection signals 402-a,
When the CPU 102 detects the High level 08-a and recognizes that the emulation operation mode is set, the emulation memory 208 is used as an access target memory.
Is fixed to the target memory control circuit 120 so that the target memory switching circuit 406 is selected.

Reference numerals 402-b and 408-b denote CPU control signals for the emulator to instruct the CPU 102 to initialize the system (LSI 100), and are output when a reset command is input from the host computer. As a result, the CPU 102 can execute the program from the program start address. In addition, the register including the target memory control register, the state of the input / output port, the state of the serial interface, etc.
Hardware specifications are initialized. In the present embodiment, the flash memory 112 is initialized so as to be accessed.

Reference numeral 402-c denotes an address bus for the emulation memory of the emulator, 402-d denotes a data bus for the emulation memory of the emulator, and 402-e denotes an access signal for the emulation memory of the emulator, which is exclusively used for reading (reading). . Also,
404-a is an address bus for flash memory;
-B is a flash memory data bus, and 404-c is a flash memory access signal. In addition, 408
-C is a memory address signal, 408-d is a memory data signal, and 408-e is a memory access signal.

As the memory interface 110,
For example, a circuit having a circuit configuration as shown in FIG. 3 can be used. In this figure, SW1 to SW8 are switches that are turned ON / OFF by a target memory switching control signal 406, and only SW5 is a bidirectional switch. 40
2-a is Hig when the emulator 200 is connected.
The signal 408-a goes high when the emulator 200 is connected, and goes low due to a pull-down resistor in the memory 110 when not connected.

When the emulator 200 is connected, the target memory switching control signal 406 becomes High level, so that SW1, SW2, SW4, SW6 and SW8
Is turned on. In this case, the CPU control signals 402-b and 408-b become valid, and the memory address signal 408-c and the memory data signal 408
−d and the memory access signal 408-e are connected to the emulator 200, and the CPU 102 can access the emulation memory 208.

On the other hand, when the emulator 200 is connected, the target memory switching control signal 406 goes low, so that SW3, SW5 and SW7 are turned on. In this case, the memory address signal 408-c, the memory data signal 408-d, and the memory access signal 408-e are connected to the flash memory 112, and
The PU 102 can access the flash memory 112.

When the emulator 200 is not connected, the target memory switching control signal 406 is always at the Low level, and the CPU 102 can access the flash memory 112.

The characteristic functions of the LSI with a built-in flash memory according to the first embodiment will be described below with reference to FIG. In this embodiment, whether to access the flash memory or the emulation memory is determined by C
The PU 102 is determined, and the CPU 102 writes the access target information to the target memory control register 104. This process is described in a program executed by the CPU 102.

In this LSI with built-in flash memory, during emulation operation, the CPU 102 reads data from the emulation memory using the emulation memory address bus 402-c, the emulation memory data bus 402-d, and the emulation memory access signal 402-e. When performing the above, the CPU 102 writes information indicating that the emulation memory is a target in the target memory control register 104. The target memory switching control signal 40 output from the target memory control circuit 120 in response to this information
6, the memory interface 110 causes the memory address signal 408-c and the memory access signal 408
-E is an emulation memory address bus 402-
c and emulation memory access signal 402-e
And outputs the program code stored in the emulation memory to the data bus 40 for the emulation memory.
2-d and output as a memory data signal 408-d. At this time, the memory interface 11
0 indicates a memory address signal 408-c and a memory access signal 4 for the flash memory address bus 404-a and the flash memory access signal 404-c.
08-e is not output.

On the other hand, the CPU 102 sets the flash memory address bus 404-a, the flash memory data bus 404-b, and the flash memory access signal 4
When reading data from the flash memory 112 using 04-c, the CPU 102 writes information indicating that the flash memory is the target in the target memory control register 104. Then, the memory interface 110 is controlled by the target memory switching control signal 406 output from the target memory control circuit 120 in response to this information.
Transmits the memory address signal 408-c and the memory access signal 408-e to the flash memory address bus 40.
4-a and a flash memory access signal 404-c, read the data stored in the flash memory 112 from the flash memory data bus 404-b, and output it as a memory data signal 408-d. At this time, the memory interface 110 responds to the emulation memory address bus 402-c and the emulation memory access signal 402-e with respect to the memory address signal 408-c and the memory access signal 408.
Do not output -e.

Further, when the CPU 102 writes data (issues a command) to the flash memory 112, the CPU 102 writes information indicating that the flash memory is to be accessed in the target memory control register 104. Then, in response to the target memory switching control signal 406 output from the target memory control circuit 120 in response to this information, the memory interface 110 causes the memory address signal 408-c and the memory data signal 408
-D and the memory access signal 408-e are output to the flash memory address bus 404-a, the flash memory data bus 404-d, and the flash memory access signal 404-c. At this time, the emulation memory access signal 402-e is not output because it is a read-only signal.

As described above, according to the LSI with a built-in flash memory according to the first embodiment, it is detected whether the operation mode is the actual operation mode or the emulation operation mode connected to the emulator. It is possible to switch between reading and writing data to and from the emulation memory in the emulator.

[Second Embodiment] FIG. 4 shows a LS with a built-in flash memory described in the first embodiment with reference to FIG.
FIG. 2 is a block diagram showing a configuration of a debugging system using I. In FIG. 4, an emulator 200 includes a host interface 202, a controller 204 including a CPU, a control program memory 206, and an RA.
An emulation memory 208 made up of M.

The emulation memory 208 is for storing basically the same contents as the flash memory 112 of the LSI 100 with built-in flash memory, and the control program memory 206 is for storing the program executed by the controller 204. It is.

The emulator 200 is connected by a bus 402 to the memory interface 110 of the LSI 100 with built-in flash memory. The host computer 300 is connected to the controller 204 via the host interface 202 and downloads data and the like.

Further, the emulator downloads the user program to the emulation memory in the emulator, and mainly performs (1) a hardware break function and a break by an arbitrary address value and data value. (2) a real-time trace function. Data bus can be captured in real time for each bus cycle. (3) Real-time counting function. Execution time of user program can be measured. (4) Execution measurement function between two points. Execution time between two points specified by event condition can be measured. 5) Forcible break function The debugger has a debug function that can forcibly stop the running user program.

The debugging system described above uses the emulation memory 208 when the CPU 102 executes the program code stored in the emulation memory 208 of the emulator 200, and the emulation memory 208 when the CPU 102 reads the data code stored in the flash memory 112. Has a function of accessing the flash memory 112. Further, the CPU 102 has a function of accessing the flash memory 112 when writing a data code (issuing a command) to the flash memory 112.

The reason for making the target memory different depending on whether the data is a program code or a data code when reading data is as follows. In the case of the program code, the program code can be debugged by using the debug function of the emulator, and in the case of the data code, the data stored in the actual flash memory can be used. The target memory is switched according to the data code. In an actual product, as shown in FIG. 5, a storage area for storing a program code and a storage area for storing a data code are mixed in a flash memory built in a flash memory LSI. At the program development stage, to debug this program code, R
Use an emulator such as OMICE. On the other hand, the data code is rewritten as needed by executing the program, and processing using the data code is executed. This embodiment enables debugging using a general-purpose ROMICE (emulator) at the program development stage,
For the data code written to the flash memory, to use the flash memory actually used,
The target memory differs depending on whether it is a program code or a data code.

Further, the reason why data is not written to the emulator is as follows. Since the emulation memory (SRAM) in the emulator and the real device (flash memory) have different write algorithms in data writing, a program for writing data to the flash memory cannot normally write to the emulation memory. When the emulation memory is substituted for the flash memory as in the prior art, the AC characteristics are different. Furthermore, if the same flash memory built into the flash memory LSI is used as the emulator memory of the emulator, data can be written to the emulator. , A custom ROMICE is required.
In the present embodiment, such a problem can be prevented by writing data to the flash memory without writing data to the emulator.
Further, a general-purpose ROMICE can be used.

FIG. 6 shows the CPU 102, the target memory control register 104, and the memory interface 1 in FIG.
10, flash memory 112 and emulator 20
FIG. 7 is a diagram for explaining connection of 0 in more detail;

The control program memory 206 of the emulator 200 contains a program for writing the contents of the emulation memory 208 to the flash memory 112 and a program for writing the contents of the flash memory 112 to the emulation memory 208. After the emulator 200 is activated, when the program code is downloaded from the host computer to the emulation memory 208, the emulation memory 2
From 08, the content is transmitted to the flash memory 112 via the memory interface 110, and the same content as the emulation memory 208 is written to the flash memory 112. In addition, serial interface 114
The program code and data code downloaded to the flash memory 112 via the
By the execution of the 0 command, the command is transmitted from the flash memory 112 to the emulation 208 via the memory 110 and is written to the emulation memory 208.

The characteristic functions of the debug system according to the second embodiment will be described below with reference to FIG.

When the emulator 200 is connected to the LSI 100 with a built-in flash memory, the CPU 10
2 is the emulation memory 20 of the emulator 200
8 to execute the program code stored in CP
Ul02 writes into the target memory control register 104 information indicating that the emulation memory is the target. Then, the memory interface 110 uses the target memory switching control signal 406 output from the target memory control circuit 120 to generate a memory address signal 408-c.
Is output to the emulation memory address bus 402-c, the memory access signal 408-e is output as the emulation memory access signal 402-e, and the program code stored in the emulation memory is transmitted to the emulation memory data bus 402-c.
The data is read out to the data bus for memory 408-d via d.
At this time, the memory interface 110 does not output the memory address signal 408-c and the memory access signal 408-e in response to the flash memory address bus 404-a and the flash memory access signal 404-c.

On the other hand, the CPU 102
12 to read the data code stored in
The PU 102 writes information indicating that the flash memory is the target in the target memory control register 104. The memory interface 110 outputs the memory address signal 408-c to the flash memory address bus 404-a and the memory access signal 408-c according to the target memory switching control signal 406 output from the target memory control circuit 120. e to the flash memory access signal 404-c to transfer the data in the flash memory 112 to the flash memory data bus 4.
The data is read out to the memory data bus 408-d via the data bus 04-b. At this time, the memory interface 110 does not output the memory address signal 408-c and the memory access signal 408-e in response to the emulation memory address bus 402-c and the emulation memory access signal 402-e.

Further, the CPU 102 writes a data code into the flash memory 112 (issues a command).
Is performed, the CPU 102 sets the target memory control register 1
04 is written with information intended for the flash memory.
The memory interface 112 uses the target memory switching control signal 406 to generate a memory address signal 408-c.
To the flash memory address bus 404-a, the memory data signal 408-d to the flash memory data bus 404-b, and the memory access signal 408-e to the flash memory access signal 404-c. Is output. At this time, the emulation memory access signal 402-e is not output because it is a read-only signal.

As described above, according to the debug system of the second embodiment, when performing an operation in which it is difficult to faithfully reproduce the flash memory actually used by the emulator, access to the flash memory is performed. Therefore, debugging using an emulator can be performed while avoiding this problem. Further, since the emulator does not perform an operation such as AC characteristics that makes it difficult to faithfully reproduce the flash memory actually used, a general-purpose memory emulator can be used. Therefore, even if the flash memory built-in LIS of the present invention is used, the conventional debugging method can be used as it is.

It should be noted that a similar debugging system can be constructed even in a system using an LSI having no built-in flash memory and a flash memory.

[0051]

As described in detail above, according to the system including the flash memory of the present invention and the LSI with built-in flash memory of the present invention, it is not necessary to develop an evaluation chip only for debugging a program. Development man-hours and development costs can be reduced, and costs can be reduced. Also, since it is possible to access the flash memory that is actually used during debugging,
It is possible to perform complete actual operation verification without any mismatch between the emulator and the actual flash memory such as AC characteristics. Further, according to the system including the flash memory and the LSI with built-in flash memory of the present invention, a general-purpose emulator can be used, so that the conventional debugging method can be followed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an LSI with built-in flash memory according to an embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of FIG. 1 in detail.

FIG. 3 is a diagram for explaining a circuit configuration example of a memory interface used in one embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a debugging system using an LSI with a built-in flash memory according to an embodiment of the present invention.

FIG. 5 is a diagram for explaining a memory space in a flash memory.

FIG. 6 is a diagram showing the configuration of FIG. 4 in detail.

7A is a diagram for explaining a configuration of an actual product, and FIG. 7B is a diagram for explaining a configuration of an evaluation chip used at the time of program debugging.

FIG. 8 is a block diagram illustrating a configuration of a conventional technique.

[Explanation of symbols]

 2 Emulator main body 4 Target board 6 Host computer 10 Host interface 12 Controller (CPU) 14 Memory for control program 16 Emulation memory (RAM) 18 Flash memory command analysis unit 20 Electrical emulation unit 22 Buffer 24 Target bus 26 Flash memory emulator adapter 28 Probe 30 Target CPU 100 LSI with built-in flash memory 102 CPU 104 Target memory control register 110 Memory interface 112 Flash memory 114 Serial interface 116 I / O port 118 SRAM 120 Target memory control circuit 200 Emulator 202 Host interface 204 Controller (CPU) 206 Control program Memory 208 Emulation memory 300 Host computer 402 External bus 402-a Operation mode detection signal 402-b CPU control signal 402-c Address bus for emulation memory 402-d Data bus for emulation memory 402-e Access signal for emulation memory 404 Internal bus 404-a flash memory address bus 404-b flash memory data bus 404-c flash memory access signal 406 target memory switching control signal 408 bus 408-a operation mode detection signal 408-b CPU control signal 408-c for memory Address signal 408-d Memory data signal 408-e Memory access signal SW1 to SW8 Switch

Claims (3)

[Claims] 1. A system including a flash memory for storing a program code or a program code and a data code, comprising: an external bus connected to an emulator capable of substituting a memory operation of the flash memory; Or an emulation operation mode to which the emulator is connected. If the operation mode detection means detects the emulation operation mode, the operation mode is connected to the flash memory. A flash memory including target memory switching means for switching between an internal bus and an external bus connected to the emulator to access the flash memory or to access the emulation memory in the emulator. Tem. 2. An LSI incorporating a flash memory for storing a program code or a program code and a data code, comprising: an external bus connected to an emulator capable of acting as a memory operation of the flash memory; Operating mode detection means for detecting whether the emulation operation mode is connected to the flash memory. The operation mode detection means detects whether the emulation operation mode is connected to the flash memory. LSI with built-in flash memory, comprising target memory switching means for switching between an internal bus and an external bus connected to an emulator to access a flash memory or to access an emulation memory in an emulator . 3. A system including the flash memory according to claim 1 or an LSI with a built-in flash memory according to claim 2, wherein a memory operation of the flash memory can be performed, and
A debugging system consisting of an emulator having a program debugging function.