JP2592064B2 - Control device for semiconductor memory cartridge - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a semiconductor memory cartridge used as an auxiliary storage device of a computer, and more particularly, to a noise voltage at the time of attaching and detaching a semiconductor memory cartridge. The present invention relates to a control device for a semiconductor memory cartridge having improved means for preventing the occurrence of bleeding.

[Conventional technology]

As an auxiliary storage device of a computer (including a personal computer, a word processor, a computer for embedded control, etc.), a semiconductor memory cartridge in which one or more semiconductor memories such as a RAM or a ROM are housed in a case is provided. It is used. When a RAM is used as a semiconductor memory, a memory backup battery is also stored. This semiconductor memory cartridge
A connector or the like is detachable from a control device for writing and reading data there, and the written data can be stored when the device is removed from the control device.

By the way, in the conventional control device, after writing or reading data in the semiconductor memory cartridge,
The control line between the MPU (microprocessor) of the control device and the semiconductor memory of the semiconductor memory cartridge is applied with the same level of voltage as when the control signal of the data read command is sent from the MPU. It prevents writing by mistake in the cartridge. At this time, since no address signal is supplied from the MPU of the control device to the semiconductor memory of the semiconductor memory cartridge via the address bus, data is not read from the semiconductor memory cartridge. The level of the control signal of this data read command is “H” or “L”, and therefore, a current flows through the control line. Also, the control unit MP
U, to the data bus and the address bus between the semiconductor memories of the semiconductor memory cartridge, the voltage of the signal line of each bit is applied in addition to the data reading and writing in the semiconductor memory cartridge. The applied voltage represents "H" or "L", but of course, the address bus does not represent an address in the semiconductor memory of the semiconductor memory cartridge. Therefore, even when a voltage of the same level as when the control signal of the data read command is supplied to the control line is applied, data is not read from the semiconductor memory cartridge. However, when a voltage is applied to the signal lines of each bit of the data bus and the address bus, when the applied voltage indicates "H", the data bus and the address bus are transferred from the control device to the semiconductor memory cartridge. When the applied voltage indicates "L", current flows from the semiconductor memory cartridge side to the control device side to the data bus and the address bus.

As described above, even when data is not written or read in the semiconductor memory cartridge, a current flows through the data bus, the address bus, and the control lines (hereinafter, these are collectively referred to as signal lines). When the semiconductor memory cartridge in the state is removed from the control device, a noise voltage is generated in a connector portion connecting the control device and the semiconductor memory cartridge. This is the same when the semiconductor memory cartridge is mounted on the control device. Since a voltage is applied to each signal line on the control device side, a noise voltage is generated at the connector.

Therefore, the noise voltage generates a signal of the same level as the control signal of the data write command on the control line, and generates an address signal representing an address in the semiconductor memory of the semiconductor memory cartridge on the address bus. In some cases, it will. In such a state, writing is performed at this address of the semiconductor memory, and the data written therein is destroyed.

In a semiconductor memory cartridge or a control device, the level is usually 5 V when the level is “H”, and around 0 V when the level is “L”. However, the noise voltage generated in the connector part may be sufficiently higher than 5 V in some cases. , 0V.
When such a noise voltage is generated, the input / output buffer of the semiconductor memory cartridge used in the range of 0 V to 5 V and the input / output buffer of the control device are destroyed.

On the other hand, there is a conventional example in which a three-state buffer circuit is used as an input / output buffer of a control device, and its gate is turned off to put the connector into a high impedance state. When the semiconductor memory cartridge is detached from the control device, the gate is in the off state, the connector of the semiconductor memory cartridge is inserted into the connector of the control device, and the semiconductor memory cartridge is completely mounted. When the semiconductor memory cartridge is removed from the control device, it is turned off immediately before the electrical connection between the semiconductor memory cartridge and the control device is disconnected. As a result, it is possible to prevent generation of a noise voltage when the semiconductor memory cartridge is attached or detached.

[Problems to be solved by the invention]

By the way, when it is intended to prevent the generation of a noise voltage at the time of attaching / detaching the semiconductor memory cartridge using the three-state buffer circuit, the position of the semiconductor memory cartridge with respect to the control device at the time of attaching / detaching the semiconductor memory cartridge. A means for detecting is required. In the above-mentioned conventional example, a mechanical, optical or electrical position detecting mechanism is provided for this purpose, and further, a circuit for controlling on / off of the gate of the three-state buffer circuit is provided. Therefore, since the scale of the entire system becomes large and the position detection of the semiconductor memory cartridge is very delicate, the configuration and arrangement of the position detection mechanism require high accuracy, and the manufacturing cost increases. As a result, the product cost will increase. Of course, it is conceivable to manually turn on and off the gate of the three-state buffer circuit. However, it is not preferable to increase the number of user operations, and there is a possibility that an erroneous operation may be performed. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory cartridge control device which solves such a problem and simplifies the configuration to prevent generation of a noise voltage when the semiconductor memory cartridge is attached and detached. It is in.

[Means for solving the problem]

In order to attain the above object, the present invention provides a semiconductor memory cartridge in which a three-state buffer circuit is used as an input / output buffer and an address signal indicating a data write / read address for the semiconductor memory of the semiconductor memory cartridge is used. Means for determining whether it is a period for executing data writing and reading are provided, and during a period other than the execution period, the gate of the three-state buffer circuit is turned off to put the connector into a high impedance state, and the control unit and the control unit are mounted on the connector. The input / output signal line to / from the semiconductor memory cartridge is electrically disconnected.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a control device for a semiconductor memory cartridge according to the present invention, wherein 1 is a control device, 2 is a semiconductor memory cartridge, 3 is an MPU, 4 is an address decode circuit, 5 is a RAM, 6 is a ROM, 7 is an input / output buffer, 8 is a semiconductor memory, 9a and 9b are connectors, 10, 10 '.
Is a data bus, 11, 11 'are address buses, 12, 12' are control lines, and 13 is a backup battery.

In FIG. 1, when the semiconductor cartridge 2 is mounted on the control device 1, the connectors 9a and 9b are connected, and the bidirectional data bus 10, address bus 11, and control line 12 of the control device 1 connect the connectors 9a and 9b, respectively. Semiconductor memory cartridge 2 through
Bidirectional data bus 10 ', address bus 11', control line
It is electrically connected to 12 '. The data bus 10, address bus 11, and control line 12 are connected to the MPU 3 and the connector 9a, respectively, and an input / output buffer 7 composed of a three-state buffer circuit is provided between them.

When writing data to the semiconductor memory 8 of the semiconductor memory cartridge 2, the MPU 3 sends a control signal of a write command to the control line 12 and an address signal for designating an address in the semiconductor memory 8 at which data is to be written to the address bus 11.
Then, the data to be written are output to the data bus 10, respectively. These are sent to the semiconductor memory 8 via the input / output buffer 7 and the connectors 9a and 9b. The semiconductor memory 8 enters a write mode by a control signal, and data is written to an address specified by an address signal. When reading data from the semiconductor memory 8, the MPU 3 outputs a control signal of a read command to the control line 12 and an address signal specifying an address in the semiconductor memory 8 at which data is to be read to the address bus 11. As a result, the data read from the designated address in the semiconductor memory 8 is output to the data bus 10 'and is taken into the MPU 3 via the connectors 9b and 9a and the input / output buffer 7.

The semiconductor memory 8 is backed up by a backup battery 13, and the data written in the semiconductor memory 8 is retained even after the semiconductor memory cartridge 2 is extracted from the control device 1.

The ROM 6 stores a program, and the MPU 3 reads the program from the ROM 6 and executes the program. The RAM 5 stores data when the MPU 3 executes this program. When reading a program from the ROM 6 and writing and reading data and the like in the RAM 5, similarly to the semiconductor memory 8, the MPU 3 sends a control signal of a write / read command to the control line 12, and sends an address signal to the address bus 11. In the case of writing data to the RAM 5, the data is output to the data bus 10, and in the case of reading from the RAM 5 and the ROM, data and programs are fetched via the data bus 10.

As described above, the MPU 3 stores the RAM 5, ROM 6, and the semiconductor memory 8
Access to the data bus 10,
Since the address bus 11 and the control line 12 are commonly used, addresses in different ranges of the address space accessible by the MPU 3 are stored in the RAM 5, ROM 6, and the semiconductor memory 8.
Is occupying.

Therefore, MPU3 is controlled by the address signal output from MPU3.
It is possible to determine which of the RAM 5, the ROM 6, and the semiconductor memory 8 is to be accessed. The address decode circuit 4 performs this determination.

Therefore, assuming that the MPU 3 outputs an address signal specifying the address of the RAM 5 to the address bus 11, the address decode circuit 4 takes in the address signal, and
The selection signals S ₁ to Akuteibu. The RAM selection signal S ₁ is R
Supplied to the select input ▲ ▼ of AM5, RAM5 can be written or read. At this time, it is supplied from the address decode circuit 4 to the secret input ▲ ▼ of the ROM 6.
The ROM selection signal S ₂ and the semiconductor memory cartridge selection signal S ₃ supplied to the gate input of the input / output buffer 7 are not active. The same applies to the ROM6, the address signal designating the address of the control line 12 to the ROM6 from MPU3 is output, ROM selection signal S ₂ supplied from the address decoding circuit 4 to select input ▲ ▼ the ROM6 to Akuteibu Thus, the program can be read from the ROM 6. At this time, the RAM selection signal S ₁ and the semiconductor memory cartridge selection signal S ₃ are not active.

When the MPU ₃ does not select the semiconductor memory cartridge 8 and the semiconductor memory cartridge selection signal S ₃ is not active (“H” level), the collector of the input / output buffer 7
The data bus 10, address buffer 11, and control line 12 on the 9a side enter a high impedance state. That is, the data bus 10, address bus 11, control line 12
Is electrically divided into the MPU 3 side and the connector 9a side. Further, it outputs an address signal for designating an address in the semiconductor memory 8 to the address bus 11 MPU 3 selects the semiconductor memory card Toritsuji 8, when the semiconductor memory card Toritsuji selection signal S ₃ is Akuteibu ( "L" level) The gate input of the input / output buffer 7 is activated, the input / output buffer is enabled, and the data bus 10, address bus 11, and control line 12 on both sides of the input / output buffer 7 are electrically connected. Thus, writing and reading of data in the semiconductor memory cartridge 2 can be performed.

Therefore, when the semiconductor memory cartridge 2 is not in the data write or read state, each signal line between the input / output buffer 7 and the semiconductor memory 8 is in a high impedance state and no current flows, so that the semiconductor memory is connected to the connectors 9a and 9b. Even if the cartridge 2 is removed from the control device 1,
No noise voltage is generated at the connectors 9a and 9b. Therefore, data destruction in the semiconductor memory 8 and circuit destruction in the control device 1 and the semiconductor memory cartridge 2 do not occur. This is the same when the semiconductor cartridge 2 and the control device 1 are mounted. Therefore,
There is no need to provide a position detecting means for the control device 1 when the semiconductor cartridge memory 2 is attached or detached. In this embodiment, an address decode circuit 4 for determining whether the semiconductor memory cartridge 2 is in a data write or read state.
However, this requires only a small scale as compared with a case where a circuit for controlling the position of the semiconductor memory cartridge 2 and the ON / OFF control of the input / output buffer 7 is added. There is no problem, and no manual operation for controlling the input / output buffer 7 when the semiconductor memory cartridge 2 is attached / detached.

〔The invention's effect〕

As described above, according to the present invention, when the semiconductor memory cartridge is attached / detached, the connector portion is reliably in the high impedance state, so that no noise voltage is generated at the time of attaching / detaching, the circuit is damaged, and the semiconductor is not damaged. Data corruption does not occur in the memory cartridge, reliability is greatly improved, and additional mechanisms such as the detection of the position of the semiconductor memory cartridge can be eliminated to reduce the size of the entire system. There is no manufacturing problem such as the configuration and arrangement accuracy that occurs when the semiconductor memory cartridge is provided. Further, when data is written to or read from the semiconductor memory of the semiconductor memory cartridge, only the address signal is generated, and the connector section is used. Becomes conductive and data writing and reading in the semiconductor memory are performed immediately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a control device for a semiconductor memory cartridge according to the present invention. 1 ... Control device, 2 ... Semiconductor memory cartridge, 3
... MPU, 4 ... Address decode circuit, 7 ... I / O buffer, 9a, 9b ... Connector, 10,10 '... Data bus, 11,11' ... Address bus, 12,12 '... Control line.

Claims (3)

(57) [Claims] 1. A controller for detachably mounting a semiconductor memory cartridge and writing and reading data to and from the mounted semiconductor memory cartridge, wherein the controller indicates data write and read addresses for the semiconductor memory of the semiconductor memory cartridge. First means for determining whether to access the semiconductor memory based on the presence or absence of an address signal; and a second means for turning on / off an input / output signal line to the semiconductor memory based on a result of the determination by the first means. A control device for a semiconductor memory cartridge, characterized in that the input / output signal line is turned on only when the semiconductor memory is accessed. 2. The control device for a semiconductor memory cartridge according to claim 1, wherein said first means is an address decoding circuit. 3. Claim (1) or (2)
2. The control device for a semiconductor memory cartridge according to claim 1, wherein the second means is a three-state input / output buffer, and is in a high impedance state except when the semiconductor memory cartridge accesses the semiconductor memory.