JPS58194186A - Removable storage device - Google Patents

Abstract

PURPOSE:To simplify the removal of a storage device and to improve the utility value as an external memory, by detecting the mounting of the storage device, attaining the transmission of data with the mounted device main body such as read/write of the storage device through the detection, providing a removal preventing means of the storage device using a signal generated at the data transmission, and protecting the stored data against the mounting and removal of the storage device. CONSTITUTION:In inserting a memory cassette 5 to a word processor main body, each connecting terminal is connected. Even if the power supply of the word processor main body is applied, when no selection signal is outputted, the inserted memory cassette 5 remains in stand-by state as it is. When the memory cassette 5 is inserted correctly and the connecting terminals VCST and GND are connected respectively, since the power supply VCC of the main body is higher in voltage than the voltage applied from a battery 52 in the cassette, hereafter the power is supplied from the main body. In inserting the memory cassette 5, a terminal S of a CPU 11 is a ground level through connecting terminals CSTiN1, 2 and the insertion of the cassette 5 is detected. Since a transistor 71 or 72 is conductive during the read/write, the removal of the memory cassette 5 is prevented with the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a storage device capable of storing necessary information and reading out the stored information, which can be detachably attached to the main body of a device such as an electronic calculator or a writing/editing device (word processor).
In the above-mentioned storage device configured as above, a probby disk, magnetic bubble, magnetic tape, or the like is usually used as an external storage device for storing necessary information and for reading the stored information. This external storage device, such as a proppy disk, is very convenient to handle because the stored contents are not lost even if it is removed.

However, it is not suitable for making the device itself smaller, lighter, and labor-saving.

In view of the above-mentioned points, the present invention provides convenient handling, miniaturization,
The present invention provides an external storage device suitable for weight reduction and labor saving. The external storage device of the present invention is composed of a CMO8RAM, and is detachably installed in the main body of the device. The external storage device (hereinafter referred to as a memory cassette) is configured to back up the CMO8RAM with a battery or the like so that its stored contents will not be lost even if it is removed from the main body of the device. If the contents of the memory are saved using a backup means such as a battery, the handling becomes very troublesome.

Therefore, according to the present invention, while being attached to the main body of the device,
Protective measures are taken to prevent the memory contents from being lost even if the power to the device is turned off or if the memory cassette is inserted or removed while the device is powered on, making it easy to handle.

Hereinafter, the memory cassette of the present invention will be explained in detail by exemplifying the case where the memory cassette of the present invention is applied to a word processor. Although the present invention will be explained using a word processor, it is not limited to this, and it goes without saying that it can be implemented in any device used as an external storage device.

FIG. 1 is a perspective view showing the appearance of a word processor to which the memory cassette of the present invention is applied. As shown in the figure, a compact word processor with portability has been realized. In the figure, 1 is a keyboard for inputting information, 2 is, for example, a liquid crystal display device for displaying inputted information, 3 is a main body of a printer unit for making hard copies, and 4 is a keyboard for making a memory cassette 5 according to the present invention removable. This is an opening provided in the word processor body. The keyboard 1 is foldably provided in the main body of the word processor, and in particular, if the keyboard 1 is folded facing the liquid crystal display 2, the word processor can be made compact as shown in FIG. Normally, in the state shown in FIG. 2, the memory cassette 5id is removed, but an opening 6 is also formed in the part of the keyboard 1 that corresponds to the memory cassette 4 so that there is no problem when the keyboard 1 is folded with the attached state. are doing. Further, although the word processor shown in the figure has a built-in printer 3, the printer may be removed to form the configuration shown in FIG. 3, thereby making the word processor more compact.

FIG. 4 is a block diagram showing the entire circuit configuration of the word processor shown in FIG. 1. In the figure, the CPU II processes text information etc. input from the keyboard 1 according to the program 12 in the program memory 7, displays it on the liquid crystal display device 2, for example, and stores the input information in the internal text memory 13. . In addition, if the input information is to be converted into kana-kanji, it is converted into kanji using the kana-kanji conversion dictionary 14, and is displayed on the display device 2 and simultaneously stored in the internal text memory 13. let Furthermore, information is written to or read from the external memory 5 according to information input from the keyboard 1.
Processing is executed via the memory cassette interface 15. When the contents of the internal text memory 8 are to be hard-copied, the printer 3 is driven to print the text. CPU II performs the above processing using keyboard 1.
The program 12 in the program memory 7 is executed in accordance with the information inputted from the program memory 7 to create and edit sentences.

As shown in FIG. 4, the external memory, that is, the memory cassette 5 includes a memo IJ5-1 for storing sentences, a memory for registering words and phrases 5-2, and a memory for kana-kanji conversion suitable for the user 5-8.
etc., but it is not limited to these.

For example, a word processor may have its program stored in the memory cassette 5 for use. Although each cassette memory 5 may be replaced and used only one, it goes without saying that a plurality of cassette memories 5 may be installed and used at the same time.

Memory cassette 5 of the present invention, for example, a cassette memo lJ5 for storing texts. -1 etc. requires at least 1 to 8 bytes of storage capacity. If this 8 is a 0MO8RAM with a byte capacity, the memory cassette 5 will be 60+X80mX1 even if a backup battery is provided.
It can accommodate approximately 0 animals. The memory cassette interface housed within the main body of the device also does not require a complicated controller such as a floppy disk or magnetic bubble, and can be realized with a simple interface described later. Dad, the power consumption is only a few μW.
~ several mW, and the main body can also be powered by a battery. Furthermore, the standby current of the memory cassette is several μA or less, and a small lithium battery can store data for about 10 years. By using the memory cassette 5 in this manner, the word processor can be made much smaller, lighter, and more power efficient than conventional word processors using floppy disks or the like.

Incidentally, the same can be said of the other memory cassettes 5-2, 5-8.

The above-mentioned text storage memory cassera) 5-1 stores the information stored in the text internal memory 13 after the text is created, if you want to use the text you have created many times or if there is a possibility of using it. be done.

Then, when necessary, the memory cassette 5-1 is inserted and the information is input into the internal text memory 13. The text storage memory cassette 5-1 is used when displaying this information on the display device 2 and correcting and inserting characters to create and edit formal texts.

In addition, the memory cassette 5-2 for word registration uses the same words and phrases often when creating sentences using a word processor, and in such cases it is troublesome to input long words and phrases every time. Therefore, in order to simplify the input of the same words, words are registered (memorized) with simple headings attached to them. As a result, from now on, just by inputting the heading, the word registration memory cassette 5-2 is used to recall the word. For example, if you add the heading rWPJ to "Word Processor", you can call up "Word Processor" next time by inputting rWPJ. Some of these registered words and phrases are used temporarily, but proper nouns such as addresses, names, and company names, as well as phrases such as greetings, are not temporary for one document, and are useful if they can be used later. It is.

Especially in Japanese word processors that use kana-kanji conversion method,
This method inputs kana characters and converts them to kanji while referring to a word dictionary, but when entering a word that is not listed in the word dictionary, it is necessary to convert each character to kanji using the Onkuni dictionary, which is time-consuming. . In such a case, use the word registration and word reading functions of the memory cassette 5-2 described above.
If you register words written in kanji using kana characters as headings,
From next time onwards, you will be able to get the required kanji notation just by entering the kana characters. This kind of function is generally called a user dictionary and has existed for a long time, but conventionally, words registered in this way were stored in an internal volatile memory (RAM), etc., so when the power of the main unit was turned off, The contents of my memory had been lost. Additionally, some devices are stored in an external memory such as a floppy disk, but this not only increases the size of the device, but also causes problems in that it takes time to register and call. By using the memory cassette 5 of the present invention, the device can be made smaller, and since, for example, CMOS RAM is used, there is no practical problem in access time. Further, since the cassette 5 is removable, the user can use a personal word registration cassette. Also, depending on the purpose, it can be used as a person's name.

There is also the advantage that special cassettes for company names, addresses, etc. can be made and used. In addition, memory cassette for storing text) 5
-1 as well, a heading is added and registered at the time of registration, and when reading, it is only necessary to input the heading.

Next, we will explain the memory cassette 5-8 for kana-kanji conversion. 14 are built-in. The normally built-in dictionary 14 contains only basic words and everyday words, and does not contain proper nouns or interrogation terms. These dictionaries vary widely depending on the users who use them, and if a dictionary that covers all of them is built-in, the memory capacity will increase, the device will become larger, and the cost will increase. Moreover, storing these dictionaries in an external storage device such as a floppy disk not only increases the size of the device but also takes time to search. In the present invention, the above-mentioned memory cassette interface 1
By inserting a ROMized proper noun and interrogation term dictionary supplied by the manufacturer into 5, processing can be performed in the same manner as the internal conversion dictionary 14, so a small and high-speed word processor can be realized.

By attaching the memory cassette 5 as described above to a word processor, writing etc. can be made easier and more convenient, and by converting the memory cassette 5, the set 5 can be made smaller than a conventional floppy disk, etc. , Handling such as replacing the memory itself A: It can be done easily.

Next, a description will be given of the configuration of the interface section of the present invention, which protects the contents of the memory from being lost when the memory cassette 5 of the present invention is inserted or removed.

FIG. 5 is a diagram showing the circuit configuration of the interface section. The memory cassette 5 has a VCSTIN for connecting to the main body side of the word processor.
l, ADB, C3TEN, C3TWR, C3TRD, D
0 with connection terminals such as TB, C3TiN2GND, etc.
The above-mentioned vcsT is a power supply terminal for supplying power from the main body side to the memory cassette 5, and GND is a ground connection terminal.

ADH is an address bus connection terminal <D for reading from or writing to the storage section of the memory cassette 5.
TB is the CP for storing (registering) information in the memory section of the addressed memory cassette 5 or for information stored in the memory section.
A connection terminal for a bidirectional data bus that transmits to the UI 1 or the storage section 51, C5TEN is a connection terminal for supplying a select signal CE for selecting the installed memory cassette 5, and C3TWR is a connection terminal for supplying a selection signal CE to the storage section of the memory cassette 5. C3TRD is a connection terminal for supplying the write signal W1 supplied via the DTB to write data, and C3TRD is a connection terminal for supplying a read signal RD for reading out information in the storage section of the memory cassette 5. This is a connection terminal for supplying a signal to detect whether or not the The reason why the connection terminals C3TiN1 and C8TiN2 are provided at both ends of the cassette 5 is to ensure reliable insertion detection of the cassette 5. CP yourself on the memory cassette 5 side
Connected to the UII S terminal. Therefore, C3TiN1
If the connection between C8TiN2 and C8TiN2 is not established, the CPU
The S terminal of No. 1 does not fall to the ground level via the resistor R1, and does not perform data transmission processing with the CPU 11/fi and the memory cassette 5.

In other words, if one (1) C3TiN1 or C8TiN2 is floating, it means that the memory cassette 5 has been inserted diagonally, and the other terminals are also floating. Each terminal is also reliably connected, and reliable insertion of the memory cassette 5 can be detected.

The memory cassette 5 includes a storage section 51 for storing information, and a backup battery 52 for storing the contents of the storage section 51.
It has The storage unit 51 connects the power supply of the battery 52 to an input terminal connected to the VCC power supply terminal and C3TRD via a diode 53 for cassette selection, writing, and reading. is supplied via resistors R8, R9, and RIO, and the standby state is set. Further, address information is input to the storage unit 51 from the connection terminal ADB through the resistor array 53 and through the address bus 54, and data is input or output from the connection terminal DTB through the resistor array 55 through the address bus 56 according to this address information. be done.

On the other hand, on the main body side of the word processor, the power supply +Vcc (7.5) is connected to the connection terminal V through the backflow prevention diode 6o.
. Connected to 8T. CPU 1 is keyboard 1
The input information is converted into address data and outputted to the ADB via an address bus 61 and an interface circuit 62. The CPU II also transmits the data to be stored (registered) to the DTB via the data bus 63 and the interface circuit 64, or reads the registration information from the storage section of the memory cassette 5, and reads the registration information from the internal text memory 1.
3. Part of the information on the address bus 61 is as follows:
A selection signal CE that is input to the decoder 65 and selects the installed memory cassette 5 is output. This selection signal CE
The interface circuits 62 and 64 are set to the operating state.

Further, the selection signal CE is supplied to one side of the gate circuit 66. Since the other input terminal of the gate circuit 66 is connected to ground, when the selection signal CE is output, the signal is output as is.

The CPU II not only outputs the above-mentioned address data or text, but also outputs a write signal WR for registering and storing the generated data in the storage unit 51 and a read signal RD for reading the stored data. These signals are input to gate circuits 67 and 68, respectively. Like the gate circuit 66, the gate circuits 67 and 68 are supplied with the selection signal CE to one input terminal, so when the selection signal CE is output, they enter the operating state and output the write signal WR and the read signal RD.

The read signal RD is also supplied to the interface circuit 64, and opens the interface circuit 64 in the direction of transmitting the information read from the storage section 51 of the memory cassette 5 to the CPU II side. Further, if the read signal RD is not output, the direction of the interface circuit 64 for transmitting data to the storage section 51 is opened, and the direction of data transmission is controlled.

The outputs of the gate circuits 66, 67, 68 are supplied to the base terminals of transistors 70, 71, 72. Transistors 70, 71, and 72 are connected to C3TRD and have their emitter terminals connected to ground. Reference numeral 69 denotes a power failure detection circuit, which detects whether the word processor itself is powered on or off or detects a power failure. The power failure detection circuit 69 includes resistors R1, R2, R3,
A voltage divided by R4° resistors R5 and R6 is supplied to the bases of each transistor 70, 71, and 72.

If the output of the gate circuit 66, 67, 68 is L#, that is, the selection signal CE is not output, even if current is supplied from the power failure detection circuit 69, the transistors 70, 71, 7
The base potential of transistor 2 becomes approximately ground level, and transistors 70, 71, and 72 are turned off. Note that the gate circuits 66, 67, and 68 use open collector outputs, and cut off the ``H'' output. In other words,
When the power failure detection circuit 69 detects a power failure or a drop in the power supply voltage Vcc, the bases of the transistors are brought to ground level or to a high impedance state, and the gate circuits 66, 67 .
At the output ('H') of transistor 68, transistors 71, . 7
2 from operating.

In order to better understand the configuration of the above-mentioned interface section, its operation will be explained. This circuit operates on the memory cassette 5 regardless of the 0N-OFF state of the power supply on the main body side.
The circuit configuration is such that the stored contents of the storage section 51 are protected even if the cassette 5 is inserted or removed, or even if the main body power is turned off while the cassette 5 is inserted. However, if the cassette 5 is inserted or removed while the memory cassette 5 is being read or written, the stored contents are not guaranteed, so the cassette must be locked or an indicator is provided to show whether it can be inserted or removed. There is. In other words, the transistor 72 or 71 is activated (ON) in the read or write state, and this is used to act on the locking mechanism to prevent the inserted memory cassette 5 from being pulled out, or to turn on the lamp and read or write. Inform the user that writing is in progress.

Now, if the memory cassette 5 is removed from the main body,
The storage unit 51 consisting of CMO8RAM is supplied with a power supply voltage Vcc for memory retention from a built-in battery 52. At this time, the input terminals for selecting, writing, and reading the memory section 51 are supplied with power from the battery 52 via resistors R8, R9, and RIO, respectively, and the address input terminals and data input/output terminals are , resistor array 53.55
The storage unit 51 is in a standby state. For the battery 52, a standby voltage of about 2V and a standby current of about 1 μA are sufficient.

On the other hand, according to the word processor itself, if the cassette is not inserted, the S terminal of the CPU II is not connected to the ground, so the CPU II does not derive address information, registration data, etc., and sends the cassette select signal via the decoder 65. Do not derive CE. Therefore, even if the main body power is turned on, the power failure detection circuit 69 supplies the operating current to the base of the transistor 70, 71, 72, but the output of the gate circuit 66, 67, 68 is 1L#. Therefore, transistor 70.71°72 is OJ'
The state becomes F, and the connection terminal C3TEN.

C3TWR and C3TRD become open. Moreover, since the select signal CE is not output, the interface circuits 62, 64 (connection terminals ADB, DTB
') is not set to an operational state and is in a high impedance state. Therefore, in this state, even if the memory cassette 5 is inserted or removed, the memory cassette 5 is maintained in the cassette side state.

Next, when the memory cassette 5 is inserted into the word processor main body, each connection terminal is connected. Here, if the word processor main body is powered off, the memory cassette 5 is maintained in a standby state. Connection terminal V. Even if S is connected, the battery 52 will not flow into the main body side by the backflow prevention diode 60. Even if the power of the word processor is turned on, if a select signal or the like is not output, the memory cassette '5 inserted as described above remains in the cassette state.

Here, if the memory cassette 5 is inserted correctly, the connection terminals V GND and STt connected to each other and the power supply VccO on the main body side are connected to the battery 52 in the cassette.
Since the voltage is higher than that supplied from the main unit, subsequent power will be supplied from the main unit. At this time, the storage section 5 of the memory cassette 5
An operating voltage of +5 V is supplied to the Vcc terminal of No. 1, and the diode 57 prevents current from flowing back to the battery 52. When the memory cassette 5 is inserted, the S terminal of the CPU II becomes ground level through C3TiN1 and C8TiN2 arranged near both ends of the connector (when no cassette is inserted, the S terminal is connected to the power supply V via the resistor R7).
Since it is tied to cc, it becomes H#. ) The insertion of the cassette S can be detected.

The CPU II enables data transmission with the memory cassette 5 by connecting the S terminal to the ground. In other words, if the information input using the keyboard 1 is for reading out text etc. registered from the inserted memory cassette 5, the CPU II
According to the program No. 2, address information specifying the storage area of the text (data) registered in the memory cassette 5, particularly in the storage section 51, is derived through the address bus 61. Part of this address information is sent to the decoder 65 (and a select signal CE for selecting the cassette is outputted. This select signal CE selects one of the inserted memory cassettes, and the interface circuit 62. 6
4 is set to the operating state. Further, the output of the gate circuit 66 is inverted from sLl to "H#", and the transistor 70 is turned OFF.
A select signal CE is supplied to the select terminal of the storage section 51 of the N memory cassette 5. In other words, the storage unit 51 is set to be readable and writable. The address information output from the CPU 11 is then sent to the interface circuit 6.
2 and is supplied to the storage unit 51 via the address bus 54 on the memory cassette 5 side. In this state, the storage section 51 has an area corresponding to the address information specified.Next, when the CPU 11 outputs a reading command, that is, a read signal RD, the transistor 72 turns ONL, and the read terminal of the storage section 51 A read signal RD is supplied to.

As a result, the text in the area specified by the address information (
data) is read out from the storage unit 51 and the data bus 56
．． It is supplied to the main body side via the resistor array 55. At this time, the interface circuit 64 enables signal transmission from the right to the left in the figure using the read signal RD, and the read text is transmitted to the text internal memory 1 via the CPU II.
3 and stored.

Further, when it is desired to record a sentence or a phrase, the information (heading, etc.) is input from the keyboard 1, the CPU II outputs the header and accordingly address information specifying the registration area, and the decoder 65 uses the inserter ( (sentences, phrases, etc.) to the data bus 63, and outputs a write signal WR for writing.

On the partial memory cassette 5 side, the storage area of the storage unit 51 is designated by the transmitted address information, and the write signal WR is supplied, so that the data transmitted via the data bus 56 is transferred to the storage unit 51. 51 in the specified area.

Writing or reading data is executed in the manner described above. Here, if the cassette 5 is pulled out during reading or writing, the storage contents of the storage unit 51 are not guaranteed, but since the transistor 71 or 72 is ON during reading or writing, this prevents the pulling out of the memory cassette 5. 0 Next, the effect of protecting the storage contents of the storage section 51 in the memory cassette when the power of the main body is turned off with the memory cassette 5 inserted will be explained. When the power supply on the main body side is turned off and the voltage of the power supply Vcc drops, the power failure detection circuit 69 is activated and its output is grounded or placed in a high impedance state. As a result, since the gate circuits 66, 67, 68 are open collector outputs, the power failure detection circuit 69 outputs the transistors 70, 71, .
If no current is supplied to the base of transistor 72, even if the gate circuit 66, 67, 68 is in the %H" state, transistors 70, 71, 72 will be OFF, and their respective outputs (C
8TEN, C3TWR, C3TRD) become open. Therefore, on the memory cassette 5 side, resistors R8, R9,
Select via R1O.

Since the voltage of, for example, the battery 52 is supplied to the write and read terminals, the storage unit 51 is in a standby state. Conversely, even when the main unit's power is turned on, the power supply Vcc remains at the specified voltage (
5V), the output of the power failure detection circuit 69 is grounded or in an open state, and the storage section 51 of the memory cassette 5 is in a standby state, similar to when the power is turned off. Then, when Vcc reaches the specified voltage, the CPU on the main unit
When I and other circuit elements start operating normally, the output of the power failure detection circuit 69 starts supplying current through resistors R1, R3, and R5. Thereafter, the memory cassette 5 can be read and written under the control of the CPU II.

As explained above, according to the removably installed storage device of the present invention, the attachment of the storage device is detected, thereby making it possible to transmit data such as reading and writing of the storage device to the main body of the attached device. A means to prevent the storage device from being pulled out is provided using the signals involved in transmission, and the stored data is protected when the storage device is inserted or removed. This simplifies the operation of attaching and detaching the storage device, increasing its utility as an external memory. can be increased. Further, according to the storage device of the present invention,
It can be more compact than a storage device such as a floppy disk, and the interface section can be simplified, so it can be attached to and removed from the main body of the device.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing the external appearance of a word processor using a removable storage device according to the present invention, and FIG.
A perspective view showing the word processor in the folded state;
FIG. 3 is a perspective view showing another embodiment of the word processor;
FIG. 4 is a block diagram showing a schematic configuration of a word processor, and FIG. 5 is a storage device (memory cassette) in the present invention.
FIG. 3 is a circuit configuration diagram showing a specific example of an in-face circuit of the attachment/detachment section. 1: Keyboard 2: Display device 3: Printer 1-\
. 4: Cabinet Q1 Ya 5: Memory cassette 51: Storage section 52: Battery 11 CPU, 65: Decoder for cassette selection 66.67° 68: Gate circuit 69;
Power failure detection circuit 70, 71, 72: ) Transistor C3
TiN1゜6 port 51■: Connection terminal for detecting cassette insertion C3TEN, C3TWR, dn1 bottom: Connection terminal for reading and writing to the storage section, etc.

Claims (1)

[Claims] 1. In a device that is provided with a storage unit that can store or read data necessary for the device, and a storage device that is equipped with a backup means and that holds the stored data, is detachably installed,
A removable device comprising a detection means for detecting attachment of the storage device to the device and enabling data transmission between the storage section and the device, and a prevention means for preventing the storage device from being pulled out when outputting a signal related to the data transmission. Storage device.