JPS6316079Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a data cassette that is detachably attached to a main unit such as an electronic register.

[Prior Art] In recent years, data cassettes have become detachably attached to main devices such as electronic registers. In this case, between the electronic register body and the data cassette, for example, "expansion" which uses the memory in the data cassette to increase the memory capacity in the electronic register body, and sales data stored in the memory in the electronic register body. A ``total'' process in which data is accumulated by data type into a data cassette, and a ``transfer'' process in which sales data by type in the electronic register body are transferred to a data cassette are executed.

As the types of data increase, the number of data cassettes inevitably increases, and the management of data cassettes becomes complicated. That is, as the number of data cassettes increases, it becomes difficult to determine which data cassette stores what type of data.

Therefore, conventionally, on the surface of the data cassette,
Labels were pasted on them, and data such as memory contents and dates were written on them by hand.

[Problems to be solved by the invention] However, with this type of data cassette, each time data is written to the memory within the data cassette, the data type, date, etc. must be written on the data cassette using a label. In addition to being troublesome, if the information is neglected, it is impossible to determine what data is stored, and there is also the problem that the information may be written incorrectly.

Furthermore, if the data cassette was used for a long period of time, there was a risk that the information written on the label surface would disappear.

This invention was developed against the background of the above-mentioned circumstances, and its purpose is to provide data that can reliably and easily determine what type of data is stored in the memory within the data cassette. The goal is to provide cassettes.

[Means for solving the problem] In a data cassette 2 that is detachably connected to a main unit 1 such as an electronic register and stores data sent from the main unit, a Connection parts (connection terminals _t1 to _t6, etc.), a display part 2a for displaying various data, and a memory 22 for storing guide data of the stored data, such as date data, store machine number, identification data, etc. , displaying the guidance data in the memory on the display unit when detached from the main unit, and displaying specific data from the main unit, such as error data and guidance data for an operator, on the display unit when attached to the main unit. Display control means (three-state buffers 23, 25, 26,
(inverter 28, address counter 24, oscillation circuit 29, etc.).

Note that the words in brackets are added for reference in order to clarify how the above-mentioned means are embodied in the embodiments.

[Function] If the date, store/machine number, type data, etc. are stored in the memory as guide data,
When the data cassette is removed from the main unit,
The guide data from the memory is read out and displayed on the display section. Additionally, when a data cassette is attached to the main unit, if data is written to the memory from the main unit, specific data from this written data will be displayed on the display, so it can also be used to display data on the main unit. can.

[Embodiment] (1) Configuration A first embodiment of this invention will be specifically described below with reference to the drawings. In FIG. 1, a mounting section 1c configured to allow a data cassette 2 to be detachably mounted is provided on a standing section 1b rising from a front operation section (keyboard) 1a of a main unit (electronic register main body) 1. There is. Further, on the front surface of the upright portion 1b, in the vicinity of the cassette mounting portion 1c, there is provided a display portion 1d for electro-optically displaying monetary data and the like digitally. Note that when the data cassette 2 is attached to the register main body 1, the display section 1d of the register main body 1 and the display section 2a provided on the front side of the data cassette 2 are located close to each other and on a straight line. ing.
Incidentally, the cassette display section 2a is constituted by a liquid crystal display device.

Next, the circuit configuration will be explained with reference to FIG. By connecting the connection terminals T ₁ to T ₆ provided on the cassette mounting portion 1c of the register body 1 and the connection terminals t ₁ to _{t 6} provided at the lower end of the data cassette 2, the data cassette can be attached to the register body 1. 2 are electrically connected. Also, provided within the register body 1 are a CPU (central processing circuit) 11, a RAM (random access memory) 12, a lock mechanism 13 for locking the data cassette 2, and the like.

The CPU 11 controls various operations according to microinstructions stored in advance, and in order to detect whether or not the data cassette 2 is attached to the register body 1, the CPU ₁₁ connects the connection terminal T1 from the line _L1 .
The data cassette 2 is output by outputting a detection signal through the connection terminals t ₁ , t ₂ , and T ₂ and inputting this detection signal as a loading signal from the line l ₂ through the connection terminals t 1 , t 2 , and T 2 in sequence.
Determine the installation status of the Further, the CPU 11 is connected to the RAM 12 and the connection terminal _T3 in a phase direction via the line _l3 , and exchanges data with the RAM12 and the connection terminal _T3 , and also via the line _l4 . address data is output to the RAM 12 and connection terminal _T4 . RAM 12 is for storing total sales data, etc., and is connected to line l ₇ from CPU 11.
The chip is designated according to the chip designation signal CS inputted via the line L6, and read/write operations are controlled according to the read/write signal R/W inputted from the CPU 11 via the line _l6 . . In addition, a chip designation signal CS is sent from the CPU 11 to the connection terminal _T5 via the line _L5 .
T ₆ has _a read/write signal R/
W is input. On the other hand, the control signal outputted from the CPU 11 via line _l8 operates the electromagnetic mechanism 13a of the locking mechanism 13 to lock the locking mechanism 1.
Controls the lock and release operations of 3.

On the other hand, the data cassette 2 is powered by a battery 21 and has a RAM 22 that stores various data.
is provided. This RAM22 is a connection terminal
Read and write operations are performed according to the read/write signal R/W from _t6 . In this case, the read/write signal R/W specifies reading when it is at a low level, and specifies writing when it is at a high level. Also, the three-state buffer 23 inserted into the address bus AB connecting the RAM 22 and the connection terminal _t4 , or the three-state buffer 25 inserted into the address bus AB connecting the RAM 22 and the address counter 24, becomes conductive. The address is specified by selectively inputting address data from the register body 1 or the address counter 24 at the appropriate timing. Also,
Data bus connecting RAM22 and connection terminal _t3
Data is exchanged with the register body 1 at the timing when the three-state buffer 26 inserted in the DB is turned on. In this case, the data read from the RAM 22 is also sent to the display unit 2a via the encoder/driver 27 and displayed. Further, the three-state buffers 23 and 26 are directly set to a conductive state, and the three-state buffer 25 is set to a conductive state or a non-conductive state according to a chip designation signal CS inputted via an inverter 28. In addition, the output of the inverter 28 is connected to the address counter 24, the oscillation circuit 29, and the encoder/driver 27.
are respectively input as operation command signals.

The address counter 24 is a ring counter with a 5-bit configuration, and the address data of hexadecimal values "0""00000" (expressed in binary notation) to "1F" and "11111" (expressed in binary notation) is sent to the oscillation circuit. It generates and outputs according to a clock signal of a predetermined frequency output from 29.

FIG. 3 shows the memory format of the cassette RAM 22, and the leading area HA has hexadecimal values of "0" to "7", "8" to "F", "10" to "17",
It has a configuration with areas HA ₁ to _{HA 4} specified by address data "18" to "1F". For example, area HA ₁ has date data, area HA ₂ has store machine number, and area HA ₃ has data. Type data is stored.

(2) Operation Next, the operation of the above embodiment will be explained. First, when performing "addition,""aggregation," or "transfer" between the register body 1 and the data cassette 2 when the data cassette 2 is attached to the register body 1, In order to access the RAM 22 in the data cassette 2, the chip designation signal CS is set to Thigh level. As a result, the three-state buffers 23 and 26 become conductive, and the three-state buffer 25 becomes non-conductive. At the same time, the output of the inverter 28 causes the address counter 24, oscillation circuit 29, and encoder/driver 27 to become inactive.
Therefore, in this state, the cassette RAM
22 is addressed under the control of the CPU 11 and becomes ready for data writing and reading in response to the read/write signal R/W. As a result, "addition", "accumulation", "transfer", etc. can be performed between the register body 1 and the data cassette 2.

After executing such processing, the RAM 22 in the data cassette 2 is accessed and date data, store machine number, and type data are written in the leading area HA. In this case, the cassette
The RAM 22 receives write designation in accordance with the read/write signal R/W, and under the control of the CPU 11, each area HA ₁ to the first area HA of the RAM 22 is
This is done by addressing HA ₄ sequentially.

Next, when the data cassette 2 is attached to the register body 1 and the cassette RAM 22 is not accessed from the register body 1,
The chip designation signal CS becomes Low level. As a result, the three-state buffers 23 and 26 become non-conductive, and the three-state buffer 25 becomes conductive. At the same time, address counter 2
4. The oscillation circuit 29 and encoder/driver 27 become operational. Therefore, from the address counter 24, “0” to “1F” expressed in hexadecimal notation
address data is sequentially output and input to the cassette RAM 22 via the three-state buffer 25, and areas HA ₁ to _{HA 4} constituting the leading area HA of the cassette RAM 22 are sequentially addressed. As a result, each area of the cassette RAM 22
The data stored in HA ₁ to _{HA 4} are sequentially read out and sent to the display section 2a via the encoder/driver 27. Note that the address counter 24
is composed of ring counters, so
Address data “0” to “1F”, “0” to “1F”
...is repeatedly output, and as a result, the cassette
Head data (data stored in the leading area HA) in the RAM 22 is repeatedly read out. Therefore, the display section 2a of the data cassette 2
For example, data as shown in FIG. 4 is displayed. In other words, the first line contains date data, and the second line contains date data.
The store machine number is displayed on the first line, and the type data is displayed on the third line.

With the data cassette 2 installed in this way, the cassette RAM 22 is transferred from the register main body 1.
When the data cassette 2 is not being accessed, the head data in the RAM 22 is always displayed on the cassette display section 2a, but if the power supply 21 is turned on even when the data cassette 2 is not installed, the head data is always displayed as described above. It will be displayed.

Next, when data from the register body 1 is to be displayed on the display section 2a of the data cassette 2 while the data cassette 2 is attached, the flow shown in FIG. 5A is executed. That is, in step _S1 , the electromagnetic mechanism 13a is activated to lock the data cassette 2 with the lock mechanism 13. Next, transfer the head data in RAM22 to main body RAM1.
2 (step S ₂ ), the display data is transferred to the first area HA of the cassette RAM 22 (step S ₃ ). As a result, the display data written to the first area HA of the cassette RAM 22 is stored when the cassette RAM 22 is not accessed from the register body 1.
It comes to be displayed on the display section 2a. in this case,
Since the main body display section 1d and the cassette display section 2a are disposed in close proximity to each other in a straight line, the cassette display section 2a can be used to display, for example, a status display such as an error or a guidance display for the operator. That would be extremely convenient.

After the predetermined data is displayed on the cassette display section 2a as described above, the flow shown in FIG. 5B is executed. First, the bed data saved in the main RAM 12 is transferred to the cassette RAM 22 and restored (step S ₁ ), and then the data cassette 2 is unlocked. As a result, the head data is returned to a state where it can be displayed on the cassette display section 2a.

In the above embodiment, the read designation circuit composed of the address counter 24 and the oscillation circuit 29 performs the following operations when the chip designation signal CS disappears.
Although it is configured to be activated, it may be activated by a mounting signal indicating the mounting state of the register main body 1 and the data cassette 2 when this signal disappears.

Furthermore, in the above embodiment, when the display data from the register main body 1 is displayed on the cassette display section 2a, the head data of the cassette RAM 22 is displayed on the main body.
However, depending on the presence or absence of the loading signal, the cassette is saved to RAM12 by the read designation circuit.
The read area of RAM may be changed. That is, if the display data from the register body is transferred to an area other than the head area of the cassette RAM, saving the head data becomes unnecessary.

In addition, in the above embodiment, display data is stored in RAM2.
However, the display data may be any data stored in the RAM 22. In this case, any desired data may be set as display data by specifying the data to be displayed.

[Effects of the invention] With this invention, the same display section can be used for displaying guide data of data stored in the data cassette and for displaying specific data from the main unit, so that the display section can be used effectively.

Furthermore, since specific data from the main device is displayed when the device is attached to the main device, the display section for displaying data from the main device can be enlarged, making it possible to display a wide variety of data.

[Brief explanation of the drawing]

The drawings show one embodiment of this invention; FIG. 1 is an external perspective view of the main unit and data cassette, FIG. 2 is a block circuit diagram thereof, and FIG. 3 is a memory format of the cassette RAM. FIG. 4 is a display state diagram of the cassette display section, and FIGS. 5A and 5B are flowcharts for explaining the operation. 1...Register body, 1c...Cassette mounting section, 2...Data cassette, 22...Cassette
RAM.

Claims (1)

[Scope of Claim for Utility Model Registration] A data cassette that is detachably connected to the main unit and stores data sent from the main unit, including a connecting part for making an electrical connection with the main unit and displaying various data. a display section for storing guidance data of the stored data; a memory for displaying guidance data in the memory on the display section when detached from the main device; display control means for displaying specific data from the display section on the display section.