JPS60205764A - Check system of memory pack - Google Patents

Abstract

PURPOSE:To recognize easily and distinctly checked contents of every prescribed range in a memory pack by checking whether the memory pack is set normally or not, and checking the internal state of the set memory pack, and reporting check results. CONSTITUTION:Whether a RAM card 12 is set or not is judged by data read/ write and ''0'' is written in a flip flop FF1 to start an internal check flow if the RAM card 12 is set. Flip flops FF2 and FF3 in an internal RAM11 are set to ''0'', and an address A of the program bottom of the program card 12 is read out, and a bottom address B is read out from a program management area, and the program card, namely, the RAM card is judged to be normal if they coincide with each other. An address C of the data bottom is read out and a bottom address D is read out from a data management area for the purpose of checking a data card 13, and the data card is judged to be normal if they coincide with each other. It is judged by A<C that setting of the program and data is normal, thus terminating the check processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for checking a memory pack used in an electronic device equipped with a memory pack attachment/detachment unit.

[Conventional technology and its problems]

Conventionally, electronic program calculators, pocket computers, electronic RAM devices, etc. have been equipped with a predetermined number of memory storage attachment/detachment mechanisms, and information stored in a memory motherboard mounted (mounted) on the mechanisms has been provided. There are devices that execute predetermined processing operations based on programs, variable data, etc.

When there is an abnormality in the storage state inside this memory pack, conventionally, unless all information such as programs and variable data set (stored) in the memory pack is cleared, the device remains usable (executable). cannot be transferred to MoP).

In addition, in the case where the user forgets to attach the pack or the pack is not attached properly, conventionally there is no instruction (notification by display, etc.) (and, of course, there is no possibility of switching to the execution mode).

In this way, in the past, when the /IP device was not installed (mounted) reliably, or when an abnormality occurred in the internal memory state of the device, there was no way to notify the device of the abnormality. There were some inconveniences in handling it.

In particular, in equipment OA where the intended users are not specified, there is a high possibility that the above-mentioned inconveniences will occur when handling including the installation and removal of memory packs, and furthermore, when the above-mentioned abnormality occurs, In this case, there was a problem in terms of the operator's reliability of the device U, either because the abnormal condition was not reported or because the device could not go into execution mode forever. Among various information, if an abnormality occurs in a part of the program or data -C
However, since the abnormality cannot be identified and the execution mode cannot be changed, all 17/information inside the tsuk must be cleared as described above, which requires a lot of effort and time. This resulted in extremely wasteful work.

[Purpose of the invention]

The present invention is considered as an anchor to the above ', 1↓lit, and is a memory hack installation (implementation)! An object of the present invention is to provide a memory pack checking method that can clearly inform an operator of the internal state of the memory pack and its internal status, and that can easily and quickly carry out recovery work in the event of an abnormality.

[Key points of the invention]

The present invention provides a mechanism for checking whether or not a memory pack is properly installed, and checking the internal state of the installed memory/mother pack, in an electronic device equipped with a memory pack attachment/detachment mechanism, and a mechanism for checking the internal state of the installed memory/mother pack. By providing a mechanism to notify the contents, it is easy to handle the memory pack and the device using the memory pack, and it is possible to easily and clearly recognize the check contents for each predetermined range in the installed memory pack, and to detect glossy abnormalities. This greatly reduces the operational burden on the operator in the event of an occurrence.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Here, the memory card to be checked is a RAM card, and the JJ? An example is given below using a computer as an example.
The situation becomes clear.

Figure 24↓1 is block 1 which shows the 41.1 configuration of the cutting section in one embodiment. In 1, 10 is a CPU that controls the entire system, and 11 is an internal oil STEAM of the CPU 10. A, n, c, and o in RAM 11 are RAM cuffs, li', + F2 r F'3 are the same fritsofronov 0, and be. I2 and 13 are +1AM car F /7T jBA 'lnot (i
Part 1 (CN) Nissou 2: "C" (SajL, 'CIL 8 to i card, here it is an ltAM car) +12 is a program card, ltA81 is a 1-ta card, and 13 is a 1-ta card. . 14 is Ghee Jinrikibu, 15 is character 1. The display section 16 is a display decoder.

77-! ,'+3. I,', し〕：Show;

17 is this solve flop DI + +)2, 13
ltAM car 1° abnormality display from each output of 3 p:tq
11 circuits, I8 is CPU 11
) and an output signal of the OR circuit 12, and outputs a dart control signal (CGl) for displaying an abnormality; 19 is an inverted output signal of the AND circuit 18; This is an inverter that obtains an inverted r-) control signal (CGz). Reference numeral 20 denotes a transfer f-) circuit interposed in the normal display data transfer path 22, which is controlled to open by an "l" level r-) control signal (CG, = "l") output from the inverter 19. 21 is a transfer r- interposed in the abnormal display data transfer path 23 between the fritz defrotz fD1+, JIDs and the display decoder 16;
The gate circuit 18 outputs a gate control signal (CG, = "l") indicating a 1" level abnormal state.
) is controlled to open.

Further, the output of the AND circuit 18 is inputted to the CPU Io as a determination signal (P) for transition to execution mode.

Figure 2 shows the memory map of the program card and the RAM cards 12 and 13, which serve as data cards, installed in the memory pack attachment/detachment machine (CN).
A is the program management area, PILO is the program control area, I) Ai'A is the data area, and DA is the data 7.
7 management area, PIZO-BOTT is the program 71 Tom, DA1 indicated by the program management area PA.
'A-JIOTi' is data dε tom indicated by data ff-c rear DA.

Each of the figures C33 to C145 is
It is a figure which shows the process 70- at the time of lAM card check.

Fir fi I','? , l fal to (cl nit
Examples of the display output at each state &!4 o'clock on the 1 dark display 7'FB t s of r(AM card check) in the above embodiment are shown.

Here, the operation of one embodiment will be explained with reference to Figures 1 to 4. CPU1. o executes the following memory check process under the internal fixed microzologram 'jul jlj when the power is off (initialization flilJ 1fft1).

ill Cr'U I O, upon input of the power-on signal, first switches the flip-flop Dir0 for abnormality display control.
After resetting 21D3 (to "0"), it is determined whether or not a RAM card is installed (Stetsuzo 81182, Figure 3).

(The determination of whether to install a 2+ RAM card is made by actually reading/writing data.
RA8 (Read data of Top-Adr of card,
Then, the r-value of the 4th mode is set in register A in the internal RAM 71 (step A2 in FIG. 4).

[3] Invert the f-column of register A in the internal RAM 11 and write the inverted data back to the RAM card (step A2 in FIG. 4).

14) Furthermore, write the Top-Adr data written in 13) above again, invert the data, and write it to RAMJ.
Set in register B in J (step A31 in Figure 4)
A4).

(5) Compare the contents of register A with the contents of Zosta B, and if they match, that is, rA = e, 1, then R
It is determined that the AM card is ``f'' (normally installed),
If they do not match, that is, (A) =) (B), it is determined that the RAM card @r (the RAM card is not properly installed) (step As in Fig. 4).

1) Here, when determining the ltAM card 141'', 8 (Top -Adr) of register 8 is returned to the RAM card 12, and internal) LAM 1 is returned.
Input "0" into the fritz 7' FF in 1 (in4 diagram As t Ay).

Further, when it is determined that the RAM card 1 is absent, the flip-flop F t K is set to "1" (step A2 in FIG. 4).

(Sword) Furthermore, ``0'' (FFs = -0'') indicates that the FF1 is in the RAM card installed state.
), enter the internal check of the RAM card shown in Figure 5 (Step Sg + 84 in Figure 3).
).

Also, flip-flop FF1 is equipped with ltAM card 7h.
When @1H (FFl=@1″) indicates that there is no state, insert 3’1″ into the flip-flop Di,
Abnormality display timing signal C8='l') is output (-
IT 3 diagrams fs5-os-6).

At this time, the AND circuit 18 sends a signal to indicate the abnormality.
h+1ill is also outputted (CG, = "l"), and this signal causes the transfer r-to circuit 21 to be in an open state. As a result, flip-flop D! .

3-bit abnormality display information C'' output from D, ,D,
'100'') is input to the display decoder 16 via the data transfer path 23, and an abnormality display message based on the decoded output is displayed on the display unit 15 (step A2 in FIG. 4).

An example of the error message displayed on the display unit 15 at this time when there is no RAM card is shown in FIG. 6 (018 shown in al). On the other hand, when the RAM card is installed (F
The internal check operation of the RAM card (0”) is performed using the internal R
AM J I's 7th Ripflotzde F! .

After setting both F3 to 44011, first check the program card (RAM card 12).

That is, first, the RAM guard 12 which becomes a program card
Search for the address of the program card (PI'tO-BOTT) and set that address in register A in the internal RAM IJ (Step A2 #B in Figure 4).
2 1B! ).

(9) Next, from the program management area (PA) of the RAM card 12, a? ) Mua 19 Res (BOTTOM
Adr) [output address] to internal RAM
(FIG. 5, STETSUNO B-4).

(II) Then, the contents of register A and register B are compared, and if they match (A=, B), it is determined that the program card, that is, the EtAAi card 12 is normal, and then 7″- Moving on to checking the tacard: Figure B5 7° B5 + By).

Also, if the contents of the register and the contents of register B do not match (A)13), set the flip-flop F2 in the internal RAM 11 to 1"', internally display the error in the program section, and then turn the data card on. Proceed to check ty (5th
121 Step Ba.

BT ) 0 (11) To check i''-taka-10, first reach the data r1 (Tom (υA'rA - Hσ1'T)) of the RAIltT card 17, which is a data card, and store the address in jf3 RAM 11. (DL')
X p C4C-k Tsutsuru (, ri 5 figure step [371 [38).

(1 BOTTOM Adr) from INAM card 13 data management area (DA)
) and sets this address in register D in the internal RAMJZ (FIG. 5, 7°B).

91 Then, the contents of register C and the contents of register D are compared, and if they match (c=n), the data card, that is, the RAM card 13 is normal.4'll i19?
Suru. Next, the content of register A and the content of register C are compared to determine whether the program card data is a much larger value, that is, whether the settings of the program and data are abnormal. If it is normal, that is, “A<C
”, the RAM card checking process ends (step B lo # 812 in FIG. 5).

Also, if the contents of register C and the contents of register D do not match (C?D), it is determined that there is an abnormality in the data card, that is, the RAM card 13, and the flip-flop Fst''l in the internal RAM IJ is ”, then compare the above registers A and C (Fig. 5 Stellaf').
81G * Bll + B11m...).

Also, #,! of the comparison between register A and register C above. r
11♂, F A > CJ, and if there is an abnormality in the settings of the program and data, the publication tiJ? When the internal IL
Flinoff I in AM tl, set fF2 and C3 to pa 1#, and check the AM car 19 (ll
! ('I 51A Steso f Il
, xz l! 31s).

+141
After completing the check process for the 7 An4 card 12.13, enter the next L'c display process flow of the check contents. 1′ old υ1 whether or not,
If it is “1”, the abnormality display 1ljlJ 1ill flip-flop knob 1) 2 is ’”1#, !i :iΔmu(
71B 3 Figure Step S.

S.).

(19 Next, check whether the contents of the 7th lipfrog F3 in the inner fitth LAM 1.1 is 1', and if it is 'l', set it to 3) 'l'
is written (Step S 1811 in Figure 3).

(11 After that, the abnormality display timing signal (S="l")
(ill' (Step S■ in Figure 3)).

This signal (S=″′1″) is applied to the flip-flop DI
+ 0 * r The output signal of the OR circuit 17 that receives each output of Ds is input to the AND circuit 18, and the output of this AND circuit 18 starts execution! 111107 signal (P)
It is sent to the CPU IO as an r-) circuit 2o and transferred as an r-to control item a (CG1/CG2).
, 21, and one of the transfer P-) circuits (20 or 21) is selectively controlled to be open. .

α force CPLI 10 is the abnormality display timing signal (S=
Immediately after the output of “1”), the execution start judgment signal (P
) is ``0#'', it is recognized that both the installed RAM cards 12 and 13 are normal, and display data indicating that it is possible to start processing is output to the normal display data transfer path 22. At this time, the f-to control signal (COx) is
1"(CG="'1"), transfer r-) circuit 2
2 is under open iuu control, the display data sent from the CPU 7o is input to the display decoder/16, and based on the decoded output, the display section 15 displays the following:
A message is displayed indicating that the start of the execution mode is the river hμ.
822)0 An example of the message displayed on the display unit 15 at this time is shown in I, 'B b l cut e).

If at least one of the defroster 7' D4 + D2 and D is outputting 1'', the AND circuit 18 outputs the dart control signal (C
G1="1") is output, and this signal causes the transfer gate circuit 21 to open, and the flip-flop DI
+ o2 + 03 The output 3-bit check display information is input to the display decoder 16 via the data transfer path 23, and a check display according to the decoding output is made on the display section 15 (see Fig. 3). Step 813
+Sth) O Here, when the 3-bit check display information input to 1:Mode decoder 4"16 is "010'(1),, D3='0', 1)2='l') , an abnormality in the program section,
and indicates whether it is cleared or not. Output the display message shown in Fig. 6 1c), 001"CDI r 02 =="Q
”.

Ds-1''), the display message of Figure 6 (dl) indicating an abnormality in the variable data section and whether it can be cleared is output, and '011''(Dl='''0'' + 02 *
03="l"), a display message shown in FIG. 6 (t+l) is output, indicating an abnormality in the program section and data section, and whether or not it can be cleared.

θ樟 According to the above display contents, when the key input section 14 inputs a specific key input (Y) instructing clearing, if the flip-flop F2 in the internal RAM I is 1#, the data area ( Clear the RAM card 13),
If flip-flop F3 is 11#, clear the program area (RAM card 12) and flip-flop F3+F! If both are @l'', both the data area and the program area are cleared (step S15+816+''', 5zz in FIG. 3).

After executing this memory clear, the display message shown in FIG. 6(a) indicating the start of transition to the execution mode is output (3
Figure step 522).

In the above-mentioned embodiment, when the mother warp is turned on, R
Although the configuration is such that the AM card check is automatically performed, the present invention is not limited to this, and for example, the configuration may be such that the AM card check is performed when a specific key is operated.

Furthermore, the two checkers for checking the RAM card installation status, program section, and variable/data section are not limited to the above example, and other configurations may be used as long as the status of each section can be recognized. It's okay.

〔Effect of the invention〕

As described in detail above, according to the memory puncture checking method of the present invention, 4Uti checks whether the memory puncture is installed normally and checks the internal state of the installed memory map. By providing a mechanism to notify the check contents, it is possible to clearly notify the mounting (mounting) state of the memory puncture and the internal state to the fourth controller, making recovery work easier and easier in the event of an abnormality. It can be done quickly.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a memory map of the RAM card in the above embodiment, and Fig. 3 is a block diagram showing an embodiment of the present invention.
5 to 5 are flowcharts showing the check processing procedure of the above embodiment, and FIGS. 6A to 6E are diagrams showing notification (display) examples of the above embodiment, respectively. 10...CPU, 11... Internal RAM, 12.13
...RAM card, 14...Key personnel department, 15...
-Display section, 16... Display decoder, 17... OR circuit, 18... AND circuit, 19... Inverter, 2
0.21...transfer? -) Circuit, 22.23...Display data transfer path, FF1. F, F2, FFs r
DB e Ilh r Ds...Flip Frog @ Applicant's agent Patent attorney Takehiko Suzue Figure 1 No. 2 Mouth No. 4 No.

Claims (1)

[Claims] In an electronic one-table device equipped with a memory plug attaching/detaching device 4I't, a first abnormality detection means for determining whether or not a memory hook is attached to the memory plug/detachable device 4I't; ,
Abnormality detection means 2 for checking the storage state in the memory or storage when no abnormality is detected by the first abnormality detection means, and abnormality notification means for notifying the detection state of each of the abnormality detection means. A method for checking a memory pack, characterized in that an abnormal state of the memory pack is notified before the main operation of a device that involves accessing the memory pack is started.